Method of treating a semi-conductor wafer

Details Method of treating a semi-conductor wafer Method of treating a semi-conductor wafer

1996-01-05

1999-01-12

Bowers, Charles

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

438758, 438759, 438624, 438787, 438902, B05D 306

Patent

active

058588809

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

This invention relates to a method for treating a semiconductor wafer and in particular, but not exclusively, to what is known as planarisation.
Our Copending International Application No. PCT/GB93/01368 (published as WO94/01885) describes two methods of depositing a short-chain polymer on a wafer to form a generally planar layer: liquid short-chain polymer having the general formula Si.sub.x (OH).sub.y or Si.sub.x H.sub.y (OH).sub.z on the wafer to form a generally planar layer. wafer in a chamber, introducing into the chamber silicon-containing gas or vapour and a compound, containing peroxide bonding, in vapour form, reacting the silicon-containing gas or vapour with the compound to form a short-chain polymer on the wafer to form a generally planar layer.
For the purpose of the description that follows wherein, these two methods will be referred to as "a method of the type described".
With the method of the type described the polymer will be in liquid form, at least to the extent that it is capable of a degree of self-levelling and, as is noted in Application No. PCT/GB93/01368, the water in the layer has to be removed at least partially, by heating. In order to prevent cracking, once a quantity of the water had been removed, a relatively thick capping layer was deposited prior to heating with the intention of providing physical stability for the polymer layer. Whilst this is advantageous it has not proved entirely successful as careful control of the process is required.


SUMMARY OF THE INVENTION

One aspect the invention consists in a method of the type described, further comprising depositing a diffusion layer on the surface of the polymer layer to allow moisture to be released from the polymer at a controlled rate.
Preferably the diffusion layer acts as a permeable membrane. In a preferred embodiment the diffusion layer is deposited at between -20.degree. and 60.degree. C. and preferably at around 0.degree. C. The diffusion layer can be deposited by Plasma Enhanced Chemical Vapour Deposition (PECVD) and may be of the order of 500 .ANG.. Once the diffusion layer is deposited, the wafer may be subjected to a preliminary heating stage prior to having a capping layer deposited. A final bake may then take place between 400.degree.-475.degree. C.
As has been mentioned in the earlier Application No.
PCT/GB93/01368 the polymer layer may be preceded by the deposition of an underlayer or seed layer.
The method can conveniently include two chambers, one being a `cold` chamber for the deposition of the polymer layer and the diffusion layer and the other being a hot chamber for the deposition of the underlayer and the capping layer.


BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be performed in various ways and a specific embodiment will now be described, by way of example, with reference to the accompanying drawings, in which:
FIG. 1 to 4 illustrates schematically the steps of a planarisation process with the exception of the deposition of the diffusion layer. FIG. 1 shows an underlayer 1, which functions as an adhesion enhancer, formed by PECVD at 300 Deg. C. FIG. 2 shows a planarising layer 2 formed by CVD at approximately 0 Deg. C. The resultant layer, exhibiting surface tension forces 3, provides planarising features. FIG. 3 shows formation of a diffusion membrane 4 of 500 .ANG. which controls the rate at which moisture escapes from the planarising layer. FIG. 4 shows formation of the capping layer 5 by PECVD at 300 Deg. C. The capping layer 5 provides mechanical stability during a later densification step.


DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIGS. 1 to 4 substantially correspond with FIGS. 3a to 3d of Application No. PCT/GB93/01368 with the exception that FIG. 3 replaces FIG. 3c of the earlier Application. Thus the explanation and variations described in the earlier Application in connection with FIGS. 1, 2 and 4 (3a, 3b and 3d) substantially stand and are hereby incorporated into this specification.
There is, however, an additional proposal that there

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