Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-03-13
2007-03-13
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10897349
ABSTRACT:
The present invention provides for determining arrival times in a circuit. An arrival time for a main signal is assigned. An arrival time for a secondary signal is assigned. It is determined whether a test is for an early arrival or for a later arrival. If the test type is for a late arrival, it is determined whether the arrival time for the secondary signal is later than for the first signal. If the test type is for an early arrival, it is determined whether the arrival time for the secondary signal is earlier than for the first signal. If the test type is for the late arrival and the arrival time for the secondary signal is later than for the first signal, assume maximum interference between the signals. If the test type is for the late arrival and the arrival time for the secondary signal is not later than for the first signal, calculate the actual interference between the signals.
REFERENCES:
patent: 5650938 (1997-07-01), Bootehsaz et al.
patent: 6370676 (2002-04-01), Hayashi et al.
patent: 6698005 (2004-02-01), Lindkvist
patent: 6700536 (2004-03-01), Wiegand
patent: 6721930 (2004-04-01), Sasaki et al.
patent: 2003/0145298 (2003-07-01), Pie et al.
patent: 2005/0065765 (2005-03-01), Visweswariah
patent: 2005/0066297 (2005-03-01), Kalafala et al.
patent: 2005/0190193 (2005-09-01), Freker et al.
patent: 2006/0048086 (2006-03-01), Pie et al.
patent: 2006/0112359 (2006-05-01), Becer et al.
patent: 2006/0195807 (2006-08-01), Foreman et al.
Soreff Jeffrey Paul
Warnock James Douglas
Carr LLP
Dinh Paul
Parihar Suchin
Rifai D'Ann
LandOfFree
Method of timing model abstraction for circuits containing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of timing model abstraction for circuits containing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of timing model abstraction for circuits containing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3762611