Electrical computers and digital processing systems: support – Digital data processing system initialization or configuration
Reexamination Certificate
2001-06-06
2002-11-12
Butler, Dennis M. (Department: 2185)
Electrical computers and digital processing systems: support
Digital data processing system initialization or configuration
C713S100000, C713S501000, C713S600000
Reexamination Certificate
active
06480954
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a programmable logic device, and in particular to a field programmable gate array in which the configurable logic blocks and the programmable routing matrices are reconfigured dynamically.
2. Description of Related Art
Programmable logic devices such as field programmable gate arrays (“FPGAsu”) are a well known type of integrated circuit and are of wide applicability due to the flexibility provided by their reprogrammable nature. An FPGA typically includes an array of configurable logic blocks (CLBs) that are programmably interconnected to each other to provide logic functions desired by a user (a circuit designer). An FPGA typically includes a regular array of identical CLBs, wherein each CLB is individually programmed to perform any one of a number of different logic functions. The FPGA has a configurable routing structure for interconnecting the CLBs according to the desired user circuit design. The FPGA also includes a number of configuration memory cells which are coupled to the CLBs to specify the function to be performed by each CLB, as well as to the configurable routing structure to specify the coupling of the input and output lines of each CLB. The FPGA may also include data storage memory cells accessible by a user during operation of the FPGA. However, unless specified otherwise, the term memory cells refers to the configuration memory cells. The Xilinx, Inc. 1994 publication entitled “The Programmable Logic Data Book” describes several FPGA products and is. herein incorporated by reference in its entirety.
One approach available in the prior art to increase the complexity and size of logic circuits has been coupling multiple FPGAs (i.e. multiple chips) by external connections. However, due to the limited number of input/output connections, i.e. pins, between the FPGAs, not all circuits can be implemented using this approach. Moreover, using more than one FPGA undesirably increases power consumption, cost, and space to implement the user circuit design.
Another known solution has been increasing the number of CLBs and interconnect structures in the FPGA. However, for any given semiconductor fabrication technology, there are limitations to the number of CLBs that can be fabricated on an integrated circuit chip of practical size. Thus, there continues to be a need to increase the number of logic gates or CLB densities for FPGAs.
Reconfiguring an FPGA to perform different logic functions at different times is known in the art. However, this reconfiguration requires the time consuming step of reloading a configuration bit stream for each reconfiguration. Moreover, reconfiguration of a prior art FPGA generally requires suspending the implementation of the logic functions, saving the current state of the logic functions in a memory device external to the FPGA, reloading the entire array of memory configurations cells, and inputting the states of the logic functions which have been saved off chip along with any other needed inputs. Each of these steps requires a significant amount of time, thereby rendering reconfiguration impractical for implementing typical circuits.
SUMMARY OF THE INVENTION
In accordance with the present invention, a programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s), wherein at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device.
The PLD switches between configurations sequentially, by random access, or on command from an external or internal signal. This switching is called “flash reconfiguration”. Flash reconfiguration allows the PLD to function in one of N configurations. In this manner, a PLD with a number M of actual configurable elements, such as configurable logic blocks (CLBs), functions as if it includes M times N effective CLBS. Thus, assuming eight configurations, the PLD implements eight times the amount of logic that it actually contains by including the additional configuration memory. By using flash reconfiguration, the CLBs of the present invention are advantageously reused dynamically, thereby reducing the number of physical CLBs needed to implement a given number of logic functions in a particular user's circuit design by the factor of the number of configurations.
In accordance with another embodiment of the present invention, a programmable logic device comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure, wherein at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice is allocated to either configuration data or user data memory.
In accordance with one embodiment of the present invention, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. In one embodiment, the device further includes a storage device for storing a plurality of intermediate states of one configurable element. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.
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Chi-Yuan Chin,
Carberry Richard A.
Johnson Robert Anders
Trimberger Stephen M.
Wong Jennifer
Butler Dennis M.
Harms Jeanette S.
Xilinx , Inc.
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