Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-12-04
2007-12-04
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
11128659
ABSTRACT:
A method for placing tiles in an integrated circuit has matched devices that includes the steps of (1) calculating a metal spacing for tiles to be placed adjacent to the matched device in the integrated circuit; (2) calculating a lateral spacing for tiles to be placed adjacent to the matched device in the integrated circuit; (3) placing tiles about the matched device based on the metal spacing and the lateral spacing; (4) performing a density test in an area around the matched device; and (5) if a density test is not satisfied in the area around the matched device, dividing the matched device into at least two subdevices and repeating, with respect to each subdevice, the steps of calculating a metal spacing, calculating a lateral spacing, and placing tiles about each subdevice. The method is further adaptable to various kinds of matched devices including poly resistors, diffused resistors, double-poly capacitors, metal-insulator-metal capacitors, and fringe capacitors.
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Drennan Patrick G.
Garrity Douglas A.
LoCascio David R.
McClellan James F.
McGowan Michael J.
Chiang Jack
Doan Nghia M.
Freescale Semiconductor Inc.
Ingrassia Fisher & Lorenz P.C.
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