Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2000-12-13
2002-12-10
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S107000, C438S110000, C438S113000, C438S118000, C438S120000, C438S122000, C438S406000, C438S455000, C438S458000, C438S459000
Reexamination Certificate
active
06492195
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing it, and particularly to a technology effective for application to a technology for grinding the back of a semiconductor substrate (semiconductor wafer) with semiconductor elements formed thereon to thereby thin the semiconductor substrate.
As semiconductor elements operated at high speed, for example, a GaAs-MESFET (Metal Semiconductor Field Effect Transistor), an HEMT (High Electron Mobility Transistor), and an HBT (Hetero Junction Bipolar Transistor) are used in a high-frequency power amplifying module built in a radio communication apparatus such as a cellular phone system.
As for these semiconductor elements, there is known one which adopts a so-called PHS (Plated Heat Sink) wherein via holes extending from the surface (main surface) of a semiconductor substrate to the back thereof are provided and conductors are provided in the via holes to electrically connect predetermined electrodes on the surface of the semiconductor substrate to a metal layer provided on the back of the semiconductor substrate, and in which the thickness of the semiconductor substrate is made thin and the length of each via hole is shortened to reduce inductance, whereby an increase in high-frequency characteristic is achieved.
A technology for thinning the semiconductor substrate to 100 &mgr;m or less has been disclosed in, for example, Japanese Patent Application Laid-Open Nos. Hei 10(1998)-294246 and Hei 5(1993)-335292. The former publication has described a method of increasing the temperature of wax to the neighborhood of a melting point after the thinning of a semiconductor substrate bonded to a reinforcing plate with wax has been completed, and peeling the semiconductor substrate from the reinforcing plate while the wax is being melted.
A technology for thinning the semiconductor substrate to 25 &mgr;m has been disclosed in Japanese Patent Application Laid-Open No. Hei 7(1995)-221051. This reference describes a GaAsFET used for ultra high-frequency applications. The GaAsFET has a PHS structure wherein a metal layer, which acts as a heat sink, is provided on the reverse side (back) of a semiconductor substrate. Further, the present reference also discloses a technology for bonding the surface of the semiconductor substrate to a protective plate such as glass with wax and thereafter the wax is melted by solvent to separate a semiconductor chip brought to a PHS structure from a glass substrate.
SUMMARY OF THE INVENTION
Thinning a semiconductor element (semiconductor chip) built in a high-frequency power amplifying module (high-frequency power amplifier) is essential for improvements in high-frequency characteristics and heat dissipation.
Conventionally, a compound semiconductor substrate (semiconductor wafer: also called simply “wafer”) such as GaAs or the like on which transistors such as a GaAs-MESFET, an HEMT, an HBT, etc. are formed, is prepared and thereafter the semiconductor wafer is fixed to a support substrate such as a glass substrate with an adhesive layer such as wax, followed by thinning of the semiconductor wafer.
(1) A method of heating and melting the wax to peel the semiconductor wafer from the glass substrate and (2) a method of melting the wax by solvent to separate the semiconductor wafer from the glass substrate have been adopted for the separation of the semiconductor wafer from the glass substrate.
In the former heating method, however, the semiconductor wafer must be separated by applying an external force thereto, and the thinned wafer is often cracked and broken, thus interfering with an improvement in yields.
In the latter solvent-based melting method, since the solvent is hard to sink in the wax, the time required to perfectly separate the semiconductor wafer from the glass substrate is spent and hence productivity is low. In the case of a wafer having a diameter of 3 inches, for example, about one week is required for its separation. Incidentally, there is known a technique (Japanese Patent Application Laid-Open No. Hei 7(1995)-37768) wherein trenches are defined in the surface of a reinforcing member (support substrate) and bubbles developed in an adhesive for bonding the reinforcing member and a wafer to each other are caused to escape to the outside through the trenches. When the reinforcing member is used for the support substrate, a manufacturing process (e.g., PHS structure manufacturing process) for effecting back processing such as plating on the back of a wafer after the thinning of the wafer to thereby form an electrode layer has the potential of melting out wax from trenches and thereby deteriorating the quality of a plated film.
An object of the present invention is to provide a technology for manufacturing a semiconductor device, which is capable of performing the thinning of a semiconductor wafer and the separation of it from a support substrate with high yields.
Another object of the present invention is to provide a technology for manufacturing a semiconductor device, which is capable of performing the thinning of a semiconductor wafer and the separation of it from a support substrate in a short time.
A further object of the present invention is to provide a method of manufacturing a semiconductor device, which is capable of manufacturing a semiconductor chip having a PHS structure with high yields and in a short time.
The above, other objects, and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
A summary of a typical one of the inventions disclosed in the present application will be described in brief as follows:
The present invention includes the steps of:
preparing a support substrate having a first surface and a second surface opposite to the first surface and having a plurality of holes extending from the first surface to the second surface, a hole-free support substrate having a first surface and a second surface opposite to the first surface, and a semiconductor wafer which has a main surface and a back opposite to the main surface, and semiconductor elements formed in each individuals of a plurality of semiconductor chip forming areas, and which has, on the main surface, an etching stopper layer comprised of a conductor electrically connected to a predetermined electrode constituting each semiconductor element, and a metal layer provided so as to overlap with a scribing area around each semiconductor chip forming area;
bonding the hole-free support substrate to the second surface of the support substrate having the holes with an adhesive layer melted by heating so as to block the holes;
bonding the main surface of the semiconductor wafer to the first surface of the support substrate having the holes with an adhesive layer melted by solvent;
thinning the back of the semiconductor wafer to a predetermined thickness by grinding and wet-etching;
selectively etching the back of the semiconductor wafer to define first trenches (separation trenches for division into pieces of semiconductor chips) which reach the metal layer formed in the scribing area, and second trenches (via holes) which reach the etching stopper layer;
forming a electrode layer on the whole range of the back of the semiconductor wafer to provide a PHS structure;
melting the adhesive layer by heating and sliding the support substrate having the holes with respect to the hole-free support substrate to thereby separate the support substrate having the holes therefrom;
supplying solvent from the second surface of the support substrate having the holes through the plurality of holes to thereby reduce adhesive power of the adhesive layer for bonding the support substrate and the semiconductor wafer to each other;
peeling a group of the semiconductor chips arranged in plate form, which are mutually connected by the electrode layer and the metal layer formed in the scribing area, from the support substrate having the holes;
bonding a support tape (ultraviolet-ray cured adhesion type r
Fukushima Kikuo
Nakanishi Masaki
Sorimachi Susumu
Yamada Hiroji
Yamashita Kiichi
Duong Khanh B.
Jr. Carl Whitehead
Mattingly Stanger & Malur, P.C.
LandOfFree
Method of thinning a semiconductor substrate using a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of thinning a semiconductor substrate using a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of thinning a semiconductor substrate using a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2951517