Method of testing redundant memory cells

Details Method of testing redundant memory cells Method of testing redundant memory cells

1992-09-09

1994-07-05

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Differential sensing

G11C 700

Patent

active

053273826

ABSTRACT:
In a single chip semiconductor memory, having independent memory areas for normal memory cells and redundant memory cells, the redundant cells are tested in a parallel or multi-bit test mode simultaneously with the normal cells they replace, by enabling the redundant memory area in response to simultaneous detection of the state of the multi-bit test mode, the presence of a programmed redundant bit for a memory cell under test, and the operative selection of the normal memory matrix.

REFERENCES:
patent: 5091884 (1992-02-01), Kagami
patent: 5113371 (1992-05-01), Hamada
patent: 5148398 (1992-09-01), Kohno

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