Method of testing IC memories

Details Method of testing IC memories Method of testing IC memories

1982-09-27

1985-11-12

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Testing

371 21, 371 28, 324158T, G11C 1140, G11C 2900

Patent

active

045532257

ABSTRACT:
In a method of testing IC memories, at first, predetermined data such as all "0" or all "1" is written into an IC memory at a normal-operation power-supply voltage, and the written data is read out and confirmed. Next, the power-supply voltage is lowered and is then returned to the normal-operation power-supply voltage after a predetermined period of time has passed in order to determine whether the stored data is in agreement with the data as initially written. When the stored data is in agreement with the initially written data, the power-supply voltage is further lowered to repeat the above-mentioned procedure. The above-mentioned procedure is further repeated when the stored data is in agreement with the initially written data and a minimum data-holding limit voltage which is capable of holding the written data is thereby determined.

REFERENCES:
patent: 3916306 (1975-10-01), Patti
patent: 4253059 (1981-02-01), Bell et al.
patent: 4335457 (1982-06-01), Early
patent: 4418403 (1983-11-01), O'Toole et al.
patent: 4503538 (1985-03-01), Fritz
Chin, "Core Storage Unit Tester," IBM Technical Disclosure Bulletin, vol. 12, No. 3, Aug. 1969, pp. 447-448.

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