Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2001-08-30
2004-06-22
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
Reexamination Certificate
active
06754857
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to memory testing technology, and more particularly, to a method of testing cache memory.
2. Description of Related Art
Cache memory is a special memory subsystem in a computer, which is used to stored a copy of the most frequently used data in the primary memory. Since cache memory is faster in access speed than primary memory, it allows an increase in data access speed, thereby making the program execution faster. When the CPU references an address in the primary memory and if that address is held in the cache memory, the data is returned to the CPU from the cache memory instead of from the primary memory. The use of cache memory can significantly enhance data access speed, thus increasing the performance of program execution. To ensure the reliability of data stored in cache memory, it is an essential step in the manufacture of cache memory to test whether the cache memory would operate correctly in read/write operations.
One conventional method for testing cache memory is to provide an additional hardware architecture to the cache memory for the implementation of the testing procedure on the cache memory. The required hardware architecture can be provided in two ways:
(1) Build-In memory Self-Test mode (BIST), which is an internal hardware architecture in the cache memory; and
(2) External hardware support, which can supply a set of special instructions to the cache memory being tested for performing simulated read/write operations on the cache memory.
One drawback to the use of additional hardware architecture to the cache memory for implementing the testing procedure, however, would require additional circuit layout space to realize, and thus is quite cost-ineffective to implement. Moreover, it would result in a slower access speed to the cache memory.
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide a new method for testing cache memory, which can be implemented without having to provide additional hardware architecture for implementing the testing procedure, so as to make the testing of the cache memory more cost-effective to implement than the prior art.
In accordance with the foregoing and other objectives, the invention proposes a new method for testing cache memory, which is based on the hit/miss and encoding of data in the cache memory to test whether the cache memory would operate normally in read/write operations.
The method of the invention is designed for use on a memory system having a primary memory unit and a cache memory unit for testing the cache memory unit to check if the cache memory unit is normal in read/write operations. The method of the invention is applicable to any kind of write operation on primary memory (including programmed direct access, or read/write operation on cache memory). In one embodiment, the method according to the invention comprises the following steps: writing a block of test data into the cache memory unit; converting the test data through a first encoding process into a first block of encoded data; writing the first block of encoded data into the primary memory unit; fetching data from the primary memory unit; converting the fetched data from the primary memory unit through a second encoding process into a second block of encoded data; and then, storing the second block of encoded data into the cache memory unit; and finally comparing either the first block of encoded data or the second block of encoded data against a predetermined block of reference data to check whether the read/write operation to the cache memory unit is normal. The cache memory unit can be embedded in a microprocessor; and no encoding process is performed during any read/write operation between the CPU (Central Processing Unit) and the cache memory.
In one preferred embodiment of the invention, the fetched data from the primary memory unit is the first block of encoded data; and the predetermined block of reference data for the first block of encoded data is obtained through a first logic operation on the test data; and the predetermined block of reference data for the second block of encoded data is obtained through a second logic operation on the fetched data from the primary memory unit.
In another embodiment, the method according to the invention comprises the following steps: writing a block of test data into the cache memory unit; converting the test data through an encoding process into a block of encoded data; writing the encoded data into the primary memory unit; fetching data from the primary memory unit; and then, storing the fetched data from the primary memory unit into the cache memory unit; and finally, comparing either the block of encoded data or the block of fetched data against a predetermined block of reference data to check whether the read/write operation to the cache memory unit is normal.
In one preferred embodiment of the invention, the fetched data from the primary memory unit is the encoded data; and the predetermined block of reference data for the block of encoded data is obtained through a first logic operation on the encoded data; and the predetermined block of reference data for the fetched data from the primary memory unit is obtained through a second logic operation on the fetched data from the primary memory unit.
In another embodiment, the method according to the invention comprises the following steps: writing a block of test data into the cache memory unit; writing the test data into the primary memory unit; fetching data from the primary memory unit; converting the fetched data from the primary memory unit through an encoding process into a block of encoded data; and storing the encoded data into the cache memory unit; and finally, comparing either the block of test data or the block of encoded data against a predetermined block of reference data to check whether the read/write operation to the cache memory unit is normal.
In one preferred embodiment of the invention, the fetched data from the primary memory unit is the test data; and the predetermined block of reference data for the block of test data is obtained through a first logic operation on the test data; and the predetermined block of reference data for the block of encoded data is obtained through a second logic operation on the fetched data from the primary memory unit.
In conclusion, the invention is characterized in that the encoding method for the write operation of data from cache memory to primary memory is different from that for the read operation of data by the cache memory from the primary memory. This feature allows the testing procedure to be performed without having to provide additional hardware architecture, allowing the testing procedure to be more cost-effective to implement than the prior art.
REFERENCES:
patent: H1741 (1998-07-01), Cruts
patent: 5831987 (1998-11-01), Spilo
De'cady Albert
Faraday Technology Corp.
J.C. Patents
Kerveros James
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