Method of testing bit lines of a memory unit

Details Method of testing bit lines of a memory unit Method of testing bit lines of a memory unit

1994-03-17

1995-03-07

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

36523004, 36523003, G11C 700

Patent

active

053964667

ABSTRACT:
A method of testing bit lines of a memory unit includes the steps of alternately writing a set of first binary values and a set of inverted first binary values to blocks having even block values and to blocks having odd block values for all storage elements within each of a plurality of blocks of the memory unit; setting the memory unit to a stressed condition; alternately reading pieces of binary data from first-row storage elements of the blocks having even block values and from final-row storage elements of the blocks having odd block values by repeatedly inverting a row value of a memory address and incrementing a block value of the memory address for each block; setting the memory unit to a normal condition; and repeating the first setting step, the alternate reading step, and the second setting step for all the columns of the plurality of the blocks.

REFERENCES:
patent: 4849937 (1989-07-01), Yoshimoto
patent: 5331594 (1994-07-01), Hotta

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