Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1999-09-13
2000-12-05
Moise, Emmanuel L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
714724, 365201, G11C 2900, G01R 3128
Patent
active
061580295
ABSTRACT:
The memory can be tested by the test circuit and is connected to the latter via data lines, address lines, and control lines. At least one of the control lines is connected via a controlled switching device. The switching device can be controlled via an external terminal of the integrated circuit, with the result that the signal characteristic on the corresponding line and thus the timing of the test can be influenced externally. The invention is particularly suitable for implementing self-tests of embedded memory cores.
REFERENCES:
patent: 4701918 (1987-10-01), Nakajima et al.
patent: 5115191 (1992-05-01), Yoshimori
patent: 5351211 (1994-09-01), Higeta et al.
patent: 5502677 (1996-03-01), Takahashi
patent: 5757705 (1998-05-01), Manning
Richter Detlev
Weigand Roland
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Moise Emmanuel L.
Stemer Werner H.
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