Method of testing a sequential access memory plane and a...

Details Method of testing a sequential access memory plane and a... Method of testing a sequential access memory plane and a...

2002-02-13

2010-02-09

Tabone, Jr., John J (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S719000, C714S720000, C714S726000, C714S732000, C714S733000, C714S736000

Reexamination Certificate

active

07661040

ABSTRACT:
The sequential access memory array is able to store p words each of n bits. Such p test words each made up of n test bits are written in the memory array, the p test words are extracted sequentially and, for each current word extracted, the n test bits that compose it are compared sequentially with n respective expected data bits before extracting the next test word.

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patent: 6571364 (2003-05-01), Maeno et al.
patent: 6751757 (2004-06-01), Biskup et al.
patent: 2 282 682 (1995-04-01), None

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