Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2001-11-08
2004-04-13
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C438S014000, C438S015000, C438S016000, C438S017000, C438S018000
Reexamination Certificate
active
06720574
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to the testing of semiconductor devices and, in particular, to the use of existing test and burn-in infrastructure for the testing of a known good die (KGD) which is a bare, unpackaged die that has been tested to the equivalent of a packaged and fully tested semiconductor device.
2. Brief Description of the Prior Art
At present, there is no good low cost and low volume approach to production of KGD that uses the existing test and burn-in infrastructure. If the semiconductor die requires burn-in to insure the reliability of the device, expensive die test carriers and special test and burn-in tooling are required for the production of KGD.
Currently, the state of the art for testing KGD devices requires that the die be temporarily held in a test jig of some form in order to establish electrical contact between the input and output (input/output) pads on the device under test (DUT) and the test instrumentation. At this level, this has previously been accomplished in the art by one of two procedures. One technique, “soft” tape automatic bonding (TAB), requires making a temporary bond to the DUT input/output pads. This can give rise to considerable damage to the pads after removal. The second method for holding the DUT in a test assembly is to use a carrier in the form of an MCM with probe tips formed from hard metal bumps. The probe tips on the modules are arranged in a pattern to exactly match the positions of the input/output pads on the DUT. The DUT is aligned with the probe tips by means of either a mechanical “alignment fence” or an optical technique. Because the probe tips are not sufficiently planarizing over the surface of the die, large forces are required in order to insure good electrical contact with every input/output pad on the die. The hard metal probe tips may damage the pads. Because of the cost associated with KGD testing and quality problems posed by the “soft TAB” and MCM methods, there is a need in the art for an improved test assembly for the testing of KGD.
SUMMARY OF THE INVENTION
In accordance with the present invention, the above described problems of the prior art are minimized.
It is apparent that an approach is desirable which can reuse the existing semiconductor package, thereby making a separate production line for the testing and burn-in of the KGD unnecessary. It would be desirable if the KGD supplied could use this approach along with the relatively small purchase of some tooling that would go into the existing package along with the dies and then manufacture of the KGD. The cost of tooling is much less than purchase of separate carriers for test and burn-in. By using the existing package and test and burn-in infrastructure, this approach would open up the low volume and low cost production of KGD for the producers of KGD. Most multichip module (MCM) programs that consume KGD operate in the small to medium volume market for KGD. These purchasers would then also have an economical source of KGD.
Briefly, a reusable package having leads thereon is provided and a silicon membrane is utilized to route the signals from the pads on the semiconductor die under test to the existing package leads. The silicon membrane interfaces with the semiconductor die through compliant bumps. The compliant bumps insure that the die always has contact to the package leads. Also, standoffs are located upon the silicon membrane polymer that insure that the compliant bumps are not over-compressed and that the aluminum bond pads upon the die are not damaged through the compression of the bump thereagainst. The compliant bump also insures that any lack of coplanarity between the die and the silicon membrane is not sufficiently significant such that the die loses contact during test and burn-in. The preferred package is assembled with the silicon membrane located in the base of the ceramic package. The height of the membrane along with the thickness of the elastomer material upon the top of the die determines the force of contact between the compliant bump and the die. The optimal force exerted by the compliant bump on the die is, for example, about 8 grams of force. The silicon membrane is accurately placed into a cavity in the package by optical alignment which is well known and the die is placed over the silicon membrane, also with optical alignment so that pads on the die contact predetermined conductive paths on the silicon membrane. Then an elastomeric spring of a predetermined thickness to provide the desired force is placed over the die. Once the elements are finally assembled, a temporary lid that matches the identical package profile is placed upon the assembly. The lid is attached with a temporary adhesive such as, for example, one that cures at 150° C. Before the package and lid are cured, the assembly stage has a built-in continuity tester that checks to make sure that the die and membrane are making contact. After the continuity check, the package is ready for cure and then transportation to the existing test and burn-in line.
The present invention utilizes the existing package for KGD production. The membranes are built up specific to the particular package and particular die revision that is currently being processed by the semiconductor supplier. The KGD uses compliant bumping technology for interconnection to the semiconductor die of, for example, the type set forth in U.S. Pat. No. 5,508,228, the contents of which are incorporated herein by reference. Standoffs are used to insure that the die bond pads are not damaged by compression and that the coplanarity between the die and silicon test membrane is maintained. The standoffs are made of polymers to insure that the die surface is not damaged. The die is placed in the package with a visual alignment tool. The tooling set, where the die is place into the existing package, includes an electrical continuity checker to insure that the die is located properly in the test carrier. The height of the silicon membrane relative to the ceramic package determines the force of the compliant bump on the semiconductor die. A lid that matches the existing package profile is attached with temporary adhesive. The lid is cured on the package and can be removed later with a knife blade action below the adhesive. The existing test handling equipment can be used for which the device under test has already been characterized. The existing burn-in tooling that the device presently uses can be used. The approach is a set up for the low volume and low cost market niche such as, for example, military products for low volume multichip module producers.
KGD using existing process infrastructure in accordance with the present invention is much more economical than using a test carrier based technology of the prior art. The user does not require set up of a special test and burn-in line to manufacture KGD and is not required to maintain separate programs for the two different lines. The only components for set up are design of the silicon membrane using existing packages and temporary lids.
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Arnold Richard W.
Beardain Weldon
Prevedel Daniel W.
Riley Donald E.
Wilson Lester L.
Brady III Wade James
Soward Ida M.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Zarabian Amir
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