Method of testing a memory

Details Method of testing a memory Method of testing a memory

2001-05-11

2004-12-07

Chase, Shelly A (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Replacement of memory spare location, portion, or segment

Reexamination Certificate

active

06829736

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a method for testing a memory array with row and column redundancy whilst keeping track of row-wise and column-wise must repair occurrencies, and a memory-based device arranged for practicing such method.
BACKGROUND OF THE INVENTION
Integrated-circuit memory chips have been growing in size over the years. Large memories, and in particular DRAMs, have suffered from low manufacturing yields. It has become common practice to provide such with spare rows and columns so that after testing these may be used as replacements. In common manufacturing practice, a 2% redundancy may triple manufacturing yield. Testing of memory arrays has become a refined art, based on presenting the array with many test stimuli with a prescribed content and in a prescribed sequence, and subsequently reading the stored content for comparison with the expected response. The combination of stimulus and expected response is often called the test pattern.
Of late, processor or other circuitry has been combined with a large amount of so-called embedded memory. The nature of such other circuitry is not critical to the present invention. For digital processing, the combination often allows a larger communication bandwidth between memory and the other circuitry, than between the memory if stand alone and the environment, both in terms of the number of wires, and in terms of bit rate per wire. In various aspects, the other circuitry would isolate the memory from the chip's surroundings. The embedded array often has more I/O bit terminals than the combination has available data pins. Hence, direct access to the array is often unfeasible. Restricting the test to an inexpensive on-chip pass/fail determination, such as through a signature-generating mechanism, would not allow to execute repair operations.
By itself, the repair poses a so-called NP-Hard Problem. The problem is to determine, for a given set of faulty bit locations in the memory, and furthermore, for given numbers of spare rows and columns, respectively, the following: whether the memory is repairable, and if so: which faulty rows and/or columns should effectively be repaired
This problem is NP-Hard inasmuch as the time complexity for finding an optimum solution is exponential in the number of spare rows and in the number of spare columns. Fortuitously, in most practical cases it is tractable due to the relatively small numbers of repair rows and repair columns involved, provided only that the full fault bit map is known. The repair strategy may thus be handled off-chip. However, due to the large number of test patterns required, parallel-to-serial conversion of the complete response patterns for external verification would appreciably slow down the execution of the test. On the other hand, storing the complete fault pattern on-chip would need a second memory of the same size as the memory under test, as well as an appreciable and expensive amount of strategy-determining logic.
Now, a particular aspect of mass testing of memory is not only to pinpoint the rows and columns that should be repaired, but also to keep track of the amount of repair necessary, and to signal as early as possible when repair capability is exceeded. Such is difficult, because a particular bit fault may be part of a row to be replaced, of a column to be replaced, or of both. During the test, optimum assignment may even change due to later detected faults.
Therefore, an improved trade-off should require only moderate extensions of the on-chip facilities, while at the other hand necessitating only little communication with the external world, whilst still providing a losslessly compressed response pattern. In particular, on-chip storage space should be kept very low. Also, the loss in manufacturing yield should be low.
SUMMARY TO THE INVENTION
In consequence, amongst other things it is an object of the present invention to provide a methodology for dynamically assessing the configuration of faults already detected to at least in part and for economically assigning the faults to repair facilities that are present according to a Must Repair Strategy, and to signal in an early manner when overall repairability cannot be guaranteed any longer.
Now therefore, according to one of its aspects, the invention is characterized according to the characterizing part of claim
1
. The invention also relates to a memory-based device being arranged for implementing a method as claimed in claim
1
. Further advantageous aspects of the invention are recited in dependent Claims.
U.S. Pat. No. 5,337,318 describes a method for tallying both rows and columns in a memory array that must be repaired, and in consequence may signal occurrence of non-repairability. The present invention however allows dynamical assignment of certain faults to either a redundant column or to a redundant row for better usage of overall repair facilities.


REFERENCES:
patent: 5317573 (1994-05-01), Bula et al.
patent: 5337318 (1994-08-01), Tsukakoshi et al.
patent: 6032264 (2000-02-01), Beffa et al.

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