Method of synchronizing phase-locked loop, phase-locked loop...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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C332S128000

Reexamination Certificate

active

06711229

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for synchronizing a phase-locked loop (PLL), a PLL and a semiconductor device provided with the PLL and more particularly to the method for synchronizing the PLL by which an internal clock is synchronized with a reference clock fed from an inside and/or outside of a semiconductor device, the PLL and the semiconductor device provided with the same.
The present application claims priority of Japanese Patent Application No. Hei11-342525 filed on Dec. 1, 1999, which is hereby incorporated by reference.
2. Description of the Related Art
Generally, as one of methods for operating, with high stability and efficiency, a large-scale and complicated digital circuit, a synchronous-type circuit design method by which all latches in a digital circuit are operated in synchronization with one clock is available. When a semiconductor device such as an LSI (Large Scale Integrated Circuit), VSLI (Very Large Scale Integrated Circuit), ULSI (Ultra Large Scale Integrated Circuit) or a like is manufactured, the above synchronous-type circuit design method is mainstream. To properly operate the digital circuit designed in accordance with such a synchronous-type circuit design, it is necessary to make all latches work with a same timing. A reason is that a deviation in timing among clocks causes inconveniences as described below. That is, for example, when a shift register is constructed of a plurality of latches connected in series, if a rise or a fall of a clock to be fed to a latch in a back stage is slightly delayed behind a rise or a fall of a clock to be fed to a latch in a front stage, since output data from the latch in the front stage changes an instant at which the latch in the back stage tries to capture output data from the latch in the front stage, there is a danger that such an erroneous operation as immediate outputting of data that should have been delayed originally, by one clock period of the clock, from the latch in the back stage occurs. This phenomenon is generally called “racing”. Moreover, in a synchronous-type semiconductor device, data is read in accordance with a data reading command fed from a CPU (Central Processing Unit) and in synchronization with an internal clock generated in synchronization with an external clock fed from outside and, therefore, if there is a deviation in the synchronization, the CPU cannot read data correctly, thus causing a malfunction of the CPU and, in turn, of an entire system.
As the semiconductor device including an LSI, VLSI, ULSI or the like becomes highly integrated and high-speed in recent years in particular, since number of latches making up the semiconductor device increases, when digital circuits are mounted on a chip of the semiconductor device, number of latches operating simultaneously increases, causing an increasing risk of occurrence of errors in reading data or of racing described above. To solve this problem, the semiconductor device provided with a PLL by which clocks to be fed to all latches are synchronized with a reference clock fed from a clock generating unit mounted outside or inside the semiconductor device, is manufactured.
Moreover, in order to respond to high-speed operations of such semiconductor devices including the LSI, VLSI, ULSI or the like in recent years, it is required that the semiconductor device should operate on the clock having a high frequency. However, if a frequency itself of the reference clock to be fed from the outside of the semiconductor device is boosted, current consumption rapidly increases. To solve this problem, a method is ordinarily employed in which a clock synchronizing to the reference clock fed from the outside of the semiconductor device having a multiplied frequency is generated by the PLL mounted inside the semiconductor device, without boosting the frequency of the reference clock.
Furthermore, since the semiconductor device including an LSI,VLSI, ULSI or the like composed of a million or more transistors has been realized, it is impossible to perform circuit design directly at a transistor level. Therefore, it is necessary to sequentially and in stages perform system design which decides operations and configurations of an entire system so that each of a CPU, ROM (Read Only Memory), RAM (Random Access Memory) or a like operates as one functional block to provide desired functions of the entire system, logical design which decides relationships among functional blocks and operations in the functional blocks in accordance with specifications decided by the system design, detailed logical design which decides combinations of logical elements including NAND gates, NOR gates, latches, counters or a like to construct each of the functional blocks and circuit design which decides characteristics of electronic circuits and devices at the transistor level to meet the circuit specifications based on the logical design. At the stage of the above logical design, the PLL is treated as one of circuit blocks constituting the functional blocks and a logical designer performs the logical design freely without taking each of characteristics of the circuit block into consideration. As described above, since the PLL is treated as one of circuit blocks and its general versatility is required, a band of an oscillation frequency of a clock must be wide and a changeable range of a multiplying factor expressing the multiplying factor of an oscillation frequency of the clock to an oscillation frequency of a reference clock must also be wide.
FIG. 10
is a schematic block diagram showing an example of configurations of a conventional PLL having a wide band of an oscillation frequency and a wide changeable range of a multiplying factor. As shown in
FIG. 10
, the conventional PLL is composed of a phase frequency comparator
1
, a charge pump
2
, a low pass filter LPF
3
, a voltage controlled oscillator (VCO)
4
and a frequency divider
5
. The PLL is to be mounted on a chip of a semiconductor device. The phase frequency comparator
1
detects a difference in a phase frequency between a reference clock CK
R
to be fed from the outside and inside of the semiconductor device and a frequency-divided clock CK
D
to be fed from the frequency divider
5
and feeds an up-clock/UCK (active-low) or a down-clock DCK (active-high) having a pulse width corresponding to a difference in the phase frequency to the charge pump
2
. The charge pump
2
permits a control current I
C
to flow out on the up-clock/UCK having a pulse width corresponding to a difference in phase frequency fed from the phase frequency comparator
1
to put charge into a capacitor constituting the LPF
3
and also permits the control current I
C
to flow in on the down-clock DCK having a pulse width corresponding to the difference in the phase frequency fed from the phase frequency comparator
1
to put accumulated charge out of the capacitor constituting the LPF
3
.
The LPF
3
, as shown in
FIG. 11
, is a secondary loop filter composed of a resistor
6
having a resistance R and a capacitor
7
having a capacitance C
1
both of which are connected in series to each other and a capacitor
8
having a capacitance C
2
which is connected in parallel to the resistor
6
and the capacitor
7
. The LPF
3
is connected between an output terminal of the charge pump
2
and a ground, and is adapted to smooth the control current I
C
and outputs it as a control voltage. The VCO
4
, when receiving 2-bit oscillation frequency band setting data DT
F
, oscillates an internal clock CK
1
having an oscillation frequency corresponding to the control voltage fed from the LPF
3
in a frequency band selected out of frequency bands which have been set, for example, in four stages and feeds it to the frequency divider
5
. The frequency divider
5
, in accordance with a multiplying factor N set based on, for example, 7-bit multiplying factor setting data DT
D
fed from a CPU (not shown), divides a frequency of the internal clock CK
I
and feeds the frequency-divided c

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