Method of stress testing memory integrated circuits

Details Method of stress testing memory integrated circuits Method of stress testing memory integrated circuits

1996-06-13

1998-12-22

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

365149, G11C 700

Patent

active

058525815

ABSTRACT:
A memory self-stress mode capable of use during wafer burn-in such as for dynamic random access memory (DRAM) integrated circuits. A burn-in power supply voltage and ground voltage delivered to a common node of a plurality of memory cell storage capacitors and to an equilibrate node coupled to bit lines. An all row high test cycles word lines between a binary low logic level and a binary high logic level, thereby stressing the dielectric of the memory cell storage capacitors by imposing stress voltages of differing polarity. A half row high test cycles alternate word lines of a word line sequence thereby stressing undesired short circuit connections between adjacent word lines.

REFERENCES:
patent: 4281449 (1981-08-01), Ports et al.
patent: 5047711 (1991-09-01), Smith et al.
patent: 5241266 (1993-08-01), Ahmad et al.
patent: 5279975 (1994-01-01), Devereaux et al.
patent: 5294776 (1994-03-01), Furuyama
patent: 5298433 (1994-03-01), Furuyama
patent: 5307010 (1994-04-01), Chiu
patent: 5391892 (1995-02-01), Devereaux et al.
patent: 5438175 (1996-01-01), Ahmad et al.
patent: 5457400 (1995-10-01), Ahmad et al.
patent: 5461328 (1995-10-01), Devereaux et al.
patent: 5489538 (1996-02-01), Rostoker et al.

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