Method of stress testing integrated circuit having memory and in

Details Method of stress testing integrated circuit having memory and in Method of stress testing integrated circuit having memory and in

1997-05-23

1999-03-16

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Testing

36523003, G11C 700

Patent

active

058838449

ABSTRACT:
An integrated circuit having enhanced testing capabilities and a method of testing an integrated circuit are provided. The integrated circuit preferably includes a substrate and a memory block on the substrate. The memory block preferably has a plurality of memory cells arranged in a plurality of rows and a plurality of columns within a defined area on the substrate, at least one bit line connected to each of the plurality of memory cells and defining a column, at least one word line connected to each of the plurality of memory cells and defining a row, and sense amplifying means connected to the at least one bit line for sensing a state of an addressed memory cell in at least one of the plurality of columns. The integrated circuit also includes a selectable stress tester on the substrate and connected to the memory block for selectively stress testing only portions of the memory block and not other portions so as to determine whether to accept or reject a memory block.

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