Method of storing information in a memory cell

Details Method of storing information in a memory cell Method of storing information in a memory cell

2000-11-27

2001-12-04

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S189050, C365S185210

Reexamination Certificate

active

06327204

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of storing information in a memory cell and, more particularly, to a method of storing information by way of single bit-line rewriting (SBR).
2. Description of the Prior Art
Recently, the demand for battery-operated devices such as hand-held communication devices or personal digital assistants has increased dramatically. Accordingly, continued effort is being made to extend the battery life of these devices. As the memory used in these hand-held communication devices gets larger, it becomes more and more important to reduce the power consumption in the memory.
In general, when reading and writing from/to a memory system by activating a word line, the active device coupled to the word line become conductive as the word line becomes active, and the passive device coupled to the active device outputs information stored therein in the form of charges by way of current-flow via the bit-line, so that a small change in the bit-line voltage level occurs. At this time, the information in the memory cell is destroyed. Thus, it is necessary to have a circuit that senses the small change in the bit-line voltage and amplifies the sensed signal, and a circuit that rewrites the amplified information to the memory cell. Most commercial dynamic random access memories (DRAMs) use sense amplifiers that are capable of differential amplification. The sense amplifiers amplify the difference in voltage between the bit-lines BL and /BL and recharge the bit-lines BL and /BL to a full Vcc level, and write this restored voltage to the memory cell. Thereafter, the word-line is deactivated and the pair of bit-lines BL and /BL that is at full Vcc level becomes precharged to half Vcc (Vcc/2) level for the next read/write operation. Thus, there is power consumption occurring from the change in voltage level in the bit lines between the precharge (Vcc/2) voltage level and full Vcc voltage level whenever a DRAM is accessed.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a method of reducing the overall power consumption in memory devices by reducing unnecessary power consumption occurring from the change of voltage levels in bit lines that are not connected to a cell, by way of implementing a structure wherein information is stored via only a bit-line that is connected to the memory cell with respect to a word-line.
To this end, a method of storing information in a memory cell having a sense amplifier that differentially amplifies a difference in voltage level between a pair of bit-lines is provided, the method comprising the steps of activating a word-line connected to the memory cell to be accessed, differentially amplifying the difference in voltage level between the pair of bit-lines coupled to the memory cell to be accessed, and selecting only one bit-line that is connected to the memory cell among the pair of bit-lines and rewriting the information via said one bit-line.


REFERENCES:
patent: 3805254 (1974-04-01), Schuur
patent: 4758987 (1988-07-01), Sakui
patent: 5243560 (1993-09-01), Amishiro et al.

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