Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Quality evaluation
Reexamination Certificate
2002-12-19
2004-09-07
Shah, Kamini (Department: 2863)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Quality evaluation
C702S181000, C702S121000
Reexamination Certificate
active
06789032
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to testing semiconductor devices and more particularly to statistical analysis applied to burn-in testing techniques.
BACKGROUND
Semiconductor manufacturers routinely test integrated circuit product in wafer and/or packaged form to screen out defects and ensure quality levels shipped to the customer/consumer. Even after such tests are performed, however, a certain quantity of parts shipped will eventually fail to function after running in a use condition for some period of time. Such parts are said to possess ‘reliability defects’; i.e. defects that are not apparent until after the parts have been ‘aged’ for some period of time. Many semiconductor manufacturers therefore use an acceleration technique called ‘burn in’ as part of their production test flow. Burn-in generally consists of exposing the part to extremes of voltage and temperature (usually high voltage and high temperature), and possibly operating the part while at these extremes. An extensive theory and practice exists that models the equivalent number of hours of use a part is ‘aged’ as a function of having been subjected to burn in. As a result, semiconductor manufacturers can use burn-in to artificially age and screen out many/most reliability defects in their products before shipping the parts to the consumer, and the consumer will then see a lower quantity of reliability fails.
Recently, two techniques for separating integrated circuits into bins with varying degrees of reliability have been described in the public literature which are included herein by reference:
1) local region yield (Barnett, Singh and Nelson, “Burn-In Failures and Local Region Yield: An Integrated Yield-Reliability Model”, VTS 2001); and
2) repair/defect count in memory ICs or embedded memory (Barnett, Singh, Nelson, “Estimating Burn-In Fallout for Redundant Memory”, ITC 2001).
In both techniques, wafer level yield information is used to make predictions about reliability behavior of different classes of die. Both techniques extend the commonly used yield model based on a negative binomial statistical distribution of defects. This yield model is characterized by parameterization of the average number of killer defects per wafer (‘lambda’), and the degree to which these defects cluster (‘alpha’). Added to this model is the ratio of latent or reliability defects to killer defects (‘gamma’).
SUMMARY OF THE INVENTION
The problem with burn-in process is that the number of parts actually possessing a reliability defect in a typical mature semiconductor process is a very small fraction of the total number of otherwise good parts (usually less than 1%, and sometimes dramatically less). On most of the product, burn-in is therefore not useful. The cost of burn-in is also becoming a larger percentage of the overall production cost as semiconductor process technology advances. This cost is increasing because newer semiconductor process technologies inherently make parts that consume more electrical power when operated at typical burn-in conditions. The problem of providing this power and maintaining the temperature of the integrated circuit makes the burn-in system more complex and costly. Therefore, methods are needed to avoid burn-in on as many parts as possible while still maintaining reasonable outgoing reliability levels.
The present invention is directed to processing of critical wafer level yield parameters and information.
Additional data from wafer or module level reliability screens (such as voltage screen or burn-in) is used to obtain the relative latent defect density (gamma). The invention is also directed to using the modeled results which are compared with actual results and applied to burn-in testing.
Others have attempted empirical methods for estimating the probability of reliability failure of a given device, given some types of wafer test information. The weakness of this type of method is that there is no linkage to known behavior of semiconductor defects, so it is difficult to have confidence that the empirical model will continue to operate correctly over time. Empirical methods also require developing some sort of history of behavior (tracking parts through wafer test through reliability screen) and so are not immediately available early in the lifetime of a product. The present invention does not suffer from either of these deficiencies.
Accordingly an object of this invention is to improve the processing wafer level yield information to obtain critical yield parameters.
Another object is using the critical yield parameters with additional data to obtain relative latent defect density.
A further object is to develop a method to reduce burn-in requirements by comparing the modeled results with actual results to improve reliability.
REFERENCES:
patent: 6154714 (2000-11-01), Lepejian
patent: 6466895 (2002-10-01), Harvey et al.
C.H. Stapper, F.M Armstrong, and K. Saji, “Integrated Circuit Yield Statistics”, Proceedings of the IEEE, vol. 86, Sep. 1988, pp. 1817-1836.
I. Koren and C.H. Stapper, “Yield Models for Defect Tolerant VLSI Circuits: A Review”, Defect and Fault Tolerance in VLSI Systems, vol. 1, 1 Koren (ed.), Plenum, 1989, pp. 1-21.
Barbour Tange N.
Barnett Thomas S.
Grady Matthew S.
Purdy Kathleen G.
International Business Machines - Corporation
Shah Kamini
Walsh Robert A.
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