Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Patent
1998-02-02
2000-03-07
Bowers, Charles
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
438788, 438108, 438633, H07L 21283
Patent
active
060339993
ABSTRACT:
A method of annealing an interlevel dielectric (IDL) layer 24 composed of PE-TEOS oxide before contact openings are formed in the ILD layer. The anneal prevents the contact openings 30 in IDL layer 24 from shifting and causing contact problems (contact oblique 33). The method begins by forming a first insulating layer 16 20 over a semiconductor structure 12. An ILD layer 24 composed of silicon oxide formed by a PECVD process using TEOS overlying the structure 12. In a key step, first rapid thermal anneal (RTA) is performed on the interlevel dielectric layer 24. The first RTA is preferably performed at a temperature in a range of between about 940 and 1100.degree. C. for a time in a range of between about 10 and 120 seconds. A contact hole 30 is then formed through the first insulating layer and the interlevel dielectric layer 24. The invention's first rapid thermal anneal prevents the ILD layer 24 from shrinking and shifting that distorts the contact hole 30.
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Chiang Min-Hsiung
Huang Jenn Ming
Lei Ming-Ta
Wu Jann-Ming
Ackerman Stephen B.
Bowers Charles
Kilday Lisa A
Saile George O.
Stoffel William J.
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