Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-11-25
2001-08-28
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S612000, C438S614000
Reexamination Certificate
active
06281106
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to circuit components and particularly surface-mount (SM) circuit devices. More particularly, this invention relates to a method of solder bumping a circuit component to yield a graded solder connection with improved standoff.
BACKGROUND OF THE INVENTION
Surface-mount (SM) semiconductor devices such as flip chips typically include an integrated circuit and beadlike terminals formed on one of their surfaces. The terminals are typically in the form of solder bumps near the edges of the chip, and serve to both secure the chip to a circuit board and electrically interconnect the flip chip circuitry to a conductor pattern on the circuit board. The circuit board may be a ceramic substrate, printed wiring board (PWB), flexible circuit or silicon substrate, though other substrates are possible. Due to the numerous functions typically performed by the microcircuitry of a semiconductor device, a relatively large number of solder bumps are required. The size of a typical flip chip is generally on the order of a few millimeters per side, resulting in the solder bumps being crowded along the edges of the chip.
Because of the narrow spacing required for the solder bumps and their conductors, soldering a flip chip or other SM component to a conductor pattern requires a significant degree of precision. Reflow solder techniques are widely employed for this purpose, and entail precisely depositing a controlled quantity of solder on the interconnect pads of the chip using methods such as electrodeposition and printing. Once deposited, heating the solder above its melting or liquidus temperature serves to form the solder bumps on the pads. After cooling to solidify the solder bumps, the chip is soldered to the conductor pattern by registering the solder bumps with their respective conductors and then reheating, or reflowing, the solder so as to form solder connections that metallurgically adhere to the conductors.
Flip chip interconnect pads are electrically interconnected with the circuitry on the flip chip through vias. Because aluminum metallization is typically used in the fabrication of integrated circuits, interconnect pads are typically aluminum or aluminum alloy, which are generally unsolderable and susceptible to corrosion if left exposed. Consequently, one or more additional metal layers are often deposited on aluminum interconnect pads to promote wetting and metallurgical bonding with solder bump alloys. These additional metal layers, or under bump metallurgy (UBM), may be, for example, electroless nickel and a top layer of gold that will readily wet and bond with typical tin-lead solder alloys. Another suitable UBM composition has a multilayer structure that includes an adhesion-promoting layer, a diffusion barrier layer, and a solderable layer. The adhesion layer may be aluminum or another metal composition that will bond to the underlying aluminum interconnect pad. Copper is readily solderable, i.e., can be wetted by and will metallurgically bond with solder alloys of the type used for solder bumps, and therefore is a common choice for the solderable (top) layer of the UBM. The diffusion barrier layer is typically a nickel-vanadium or chromium-copper alloy, and is disposed between the adhesion and solderable layers to inhibit diffusion between the solder and aluminum pad. A NiV and CrCu layer also serves as a wettable layer if an overlaying copper layer is dissolved into the solder.
FIG. 1
depicts a prior art surface-mount assembly, in which an interconnect pad
112
of a flip chip
110
is electrically and mechanically connected with a solder connection
114
to a conductor
116
on a substrate
118
. As shown, the assembly includes a UBM
120
deposited within an opening in a passivation layer
122
formed on the surface of the chip
110
to provide protection from environmental contaminants, moisture and electrical shorts. The solder connection
114
has a shape slightly wider than spherical, characteristic of a reflowed solder bump of any alloy, such as the eutectic 63Sn/37Pb solder alloy (melting point of 183° C.) and near-eutectic Sn-Pb solder alloys widely used for flip chip assemblies. As used herein, a near-eutectic alloy has physical and mechanical properties very near that of the eutectic alloy.
Placement of the chip and reflow of the solder must be precisely controlled not only to coincide with the spacing of the interconnect pads and the conductors to which the solder bumps are registered and reflow soldered, but also to control the height and width of the solder connections after reflow. As would be expected, controlling the width of the solder connections is necessary to prevent shorting between adjacent connections. As is also well known in the art, controlling the height of solder connections after reflow is often necessary to prevent the molten solder from drawing the flip chip excessively close to the substrate during the reflow operation, when the molten solder bump tends to spread outward as a result of wetting the surfaces it contacts. Sufficient spacing between the chip and its substrate, often termed the “standoff,” is desirable for enabling stress relief during thermal cycles, allowing penetration of cleaning solutions for removing undesirable processing residues, and enabling the penetration of mechanical bonding and underfill materials between the chip and certain substrate materials.
Control of solder bump height and width are determined in part by the amount and composition of the solder deposited on the interconnect pads of a flip chip. The amount of solder can be closely controlled by known deposition methods. However, as evident from
FIG. 1
, as solders are reflowed they tend to collapse, forming spherically-shaped solder connections
120
with limited standoff. The standoff possible with a reflowed solder bump is also reduced by the tendency for the solder to flow out over the conductors during reflow, reducing the volume of solder directly between the interconnect pad and substrate. High melting point (MP) solders have been used on die to improve standoff following die assembly by solder reflow. Before assembly, a relatively high MP solder is reflowed on the die, and a lower MP solder is applied to the substrate to which the die is to be attached. For the assembly operation, a reflow temperature is chosen such that the low MP solder reflows to join the high MP solder (and therefore, the die) to the substrate, but the high MP solder does not melt and collapse. As a result, the high MP solder is able to substantially maintain the pre-reflow standoff of the assembly. However, there is a cost disadvantage to placing solder on the substrate prior to assembly, especially for devices with pad pitches of 250 micrometers and less.
From the above it can be seen that it would be desirable if an improved method were available for forming solder bumps on flip chips and other SM semiconductor devices that employ solder bumps, by which such devices could be reflow soldered to yield solder connections of a more columnar nature and with greater standoff while also being compatible with typical process temperature constraints of SM processes.
SUMMARY OF THE INVENTION
According to this invention, a method is provided for solder bumping a SM circuit component, as well as electrically and mechanically connecting the component to a conductor on a substrate, and the components and assemblies formed thereby. The method of this invention promotes the formation of solder connections with sufficient height to enable stress relief during thermal cycles, allow penetration of cleaning solutions beneath the circuit component, and enable the penetration of mechanical bonding and underfill materials between the component and substrate, while also being compatible with process temperature limitations that typically exist for surface-mount devices and substrate materials.
The method generally entails forming a multilayer metal bump containing discrete layers, including at least one layer of a solder alloy, a first metallic la
Higdon William David
Stepniak Frank
Yeh Shing
Delphi Technologies Inc.
Everhart Caridad
Funke Jimmy L.
LandOfFree
Method of solder bumping a circuit component does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of solder bumping a circuit component, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of solder bumping a circuit component will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2471342