Semiconductor device manufacturing: process – Semiconductor substrate dicing – By electromagnetic irradiation
Reexamination Certificate
2001-03-01
2002-06-04
Niebling, John F. (Department: 2827)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
By electromagnetic irradiation
C438S113000, C438S114000, C438S460000, C438S462000, C438S465000
Reexamination Certificate
active
06399463
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to electronic components and electronic component packaging. More particularly, the present invention relates to a method of singulating electronic components from a wafer.
BACKGROUND OF THE INVENTION
As is well known to those of skill in the art, integrated circuits, i.e., electronic components, are fabricated in an array on a wafer. The wafer is then cut, sometimes called diced, to singulate the integrated circuits from one another.
The surface of a wafer that includes the circuitry or other functional components is called the “front-side” or “first surface” of a wafer and the opposite surface of the wafer, the surface that has no functional components or circuitry, is called the “back-side” or “second surface” of the wafer. In the prior art, individual integrated circuits were singulated from wafers using either front-side or back-side cutting.
FIG. 1
is a cross-sectional view of a section of a wafer
10
being cut from a front-side surface
10
F of wafer
10
in accordance with the prior art using front-side singulation methods. According to prior art front-side singulation methods, integrated circuits
12
were formed in wafer
10
and were delineated by scribe lines
14
, which included a first scribe line
14
A and a second scribe line
14
B, on front-side surface
10
F of wafer
10
. Scribe lines
14
were formed by methods well known to those of skill in the art. For example, scribe lines
14
were often formed by selective etching of a silicon oxide layer
18
on front-side surface
10
F.
To illustrate, first scribe line
14
A delineated a first integrated circuit
12
A from a second integrated circuit
12
B. As shown in
FIG. 1
, each scribe line
14
had a width WF.
According to prior art front-side singulation methods, a back-side surface
10
B of wafer
10
was attached to a tape
20
. Wafer
10
was then sawed completely through with a saw blade
22
. Saw blade
22
was aligned with scribe lines
14
using an optical alignment system in a well-known manner. In this manner, integrated circuits
12
were singulated. According to prior art methods, tape
20
was used to support wafer
10
during sawing and to support the singulated integrated circuits
12
after sawing was complete.
Using prior art front-side singulation methods, width WF of scribe lines
14
had to be sufficiently large to accommodate: the width of saw blade
22
; the inexact positioning and alignment of saw blade
22
; the mechanical wobbling of saw blade
22
; and the uneven or rough surfaces resulting from the mechanical nature of the cutting using saw blade
22
. Stated another way, width WF of scribe lines
14
had to be large enough that the saw cut made by saw blade
22
was always within a scribe line
14
. For example, saw blade
22
is within scribe line
14
B in FIG.
1
.
The optical alignment system of the prior art used scribe lines
14
directly to align saw blade
22
and saw blade
22
was aligned to scribe lines
14
to within a mechanically mandated tolerance. To accommodate this tolerance, and the other factors discussed above that are associated with any sawing processes, scribe lines
14
were made significantly wider than saw blade
22
. To illustrate, the typical width of saw blade
22
was between 0.001 inches (0.026 mm) and 0.002 inches (0.051 mm) while width WF of scribe line
14
was typically within the range of 0.003 inches (0.077 mm) to 0.008 inches (0.203 mm).
Disadvantageously, forming scribe lines
14
with relatively large widths WF resulted in less integrated circuits
12
for any given size wafer
10
than could be formed with smaller, more optimal, scribe line widths. This was because larger widths WF meant scribe lines
14
took up more wafer surface
10
F area. This, in turn, meant more wasted wafer surface
10
F area and less surface
10
F area available for integrated circuits
12
. Consequently, the integrated circuit
12
yield per wafer
10
decreased. As a result, the cost of each integrated circuit
12
from wafer
10
was increased. Unfortunately, in today's highly competitive markets it is very important to minimize the cost of each integrated circuit
12
to remain competitive.
In certain instances, such as integrated circuits that include micro-machines or other delicate functional components, it is important to protect the front-side surface of the wafer during sawing from the pressure and shards and particulates generated during sawing. In these instances, prior art back-side singulation methods were used to saw the wafer from the back-side surface of the wafer. However, using prior art back-side singulation methods required even larger scribe line widths and resulted in even lower integrated circuit yield per wafer.
FIG. 2
is a cross-sectional view of a section of a wafer
30
being cut from a back-side surface
30
B of wafer
30
in accordance with the prior art. To protect a front-side surface
30
F of wafer
30
, front-side surface
30
F was attached to a tape
32
. Tape
32
supported wafer
30
during sawing.
Saw blade
22
was aligned with scribe lines
14
-
1
on front-side surface
30
F of wafer
30
using a two-step process. First, tape
32
was aligned with scribe lines
14
-
1
. Then, front-side surface
30
F was attached to tape
32
. Tape
32
had a surface area greater than the area of front-side surface
30
F such that tape
32
had an exposed region, which extended beyond wafer
30
. Tape
32
had alignment marks in the exposed region of tape
32
. As an example, see alignment holes
30
a
and
30
b
of Roberts, Jr. et al., U.S. Pat. No. 5,362,681, which is herein incorporated by reference in its entirety. In the above manner, scribe lines
14
-
1
were aligned with the alignment marks of tape
32
.
Second, saw blade
22
was aligned with the alignment marks of tape
32
. Wafer
30
was then sawed with saw blade
22
from back-side surface
30
B. However, since saw blade
22
was aligned indirectly to scribe lines
14
-
1
using alignment marks of tape
32
, a large tolerance, associated with the alignment of saw blade
22
to scribe lines
14
-
1
, was required.
To accommodate this large tolerance, each of scribe lines
14
-
1
had a relatively large width WB. More particularly, referring now to
FIGS. 1 and 2
together, width WB of scribe lines
14
-
1
of wafer
30
, that was designed to be cut from back-side surface
30
B, was significantly larger than width WF of scribe lines
14
of wafer
10
, which was designed to be cut from front-side surface
10
F. To illustrate, width WB was typically at least 0.012 inches (0.305 mm), and often even larger.
As with scribe line
14
discussed above, forming scribe lines
14
-
1
with relatively large widths WB resulted in less integrated circuits
12
for any given size wafer
30
. In the particular case of scribe lines
14
-
1
on wafer
30
in
FIG. 2
, the scribe lines
14
-
1
are even thicker than scribe lines
14
in FIG.
1
and the number of integrated circuits
12
is even less than the corresponding number of integrated circuits
12
formed in the same size wafer
10
in FIG.
1
. Consequently, using prior art back-side cutting as shown in
FIG. 2
resulted in an even smaller yield of integrated circuits
12
from wafer
30
. As a result, the cost of each integrated circuit
12
from wafer
30
was even greater than the cost of each integrated circuit
12
from wafer
10
.
As discussed above, both front-side and back-side prior art methods of singulation wasted large amounts of wafers
10
and
30
. This waste was necessary, using prior art methods, in order to create scribe lines
14
and
14
-
1
with widths WF and WB large enough to accommodate: the width of saw blade
22
; the inexact positioning and alignment of saw blade
22
; the mechanical wobbling of saw blade
22
; and the uneven or rough surfaces resulting from the mechanical nature of cutting using saw blade
22
.
As also discussed above, forming scribe lines
14
or
14
-
1
with relatively large widths WF and WB, as required in the prior art,
Glenn Thomas P.
Hollaway Roy Dale
Webster Steven
Amkor Technology Inc.
Gunnison McKay & Hodgson, L.L.P.
McKay Philip J.
Niebling John F.
Zarneke David A
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