Method of singulating a batch of integrated circuit package...

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S462000, C438S464000

Reexamination Certificate

active

06281047

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit packaging technology, and more particularly, to a method of singulating a combined batch of small-scale integrated circuit package units, such as TFBGA (Thin & Fine Ball Grid Array) or QFN (Quad Flat Non-leaded) package units, that are constructed on a single matrix base, without leaving remnant portions of provisional bars, such as electroplating bars or connect bars, in the singulated package units that would otherwise cause short-circuiting to the enclosed semi-conductor chips.
2. Description of Related Art
Small-scale integrated circuit packages are typically fabricated in batch on a single base predefined with a matrix of package sites, each package site being used for the fabrication of one single package unit. After encapsulation is completed, it is required to performed a singulation process so as to singulate each individual package unit from the matrix base. TFBGA (Thin & Fine Ball Grid Array) and QFN (Quad Flat Non-leaded) packages, are typically fabricated in this way.
In the case of TFBGA, a substrate predefined with a matrix of package sites (hereinafter referred to as “matrix substrate”) is used for the fabrication of a batch of TFBGA package units. The TFBGA matrix substrate is typically formed with a grid-like electroplating bar along the borderlines of the package sites, for the purpose of facilitating the required electroplating to the electrically-conductive traces on the TFBGA matrix substrate. The final singulation process is typically performed by cutting into the provisional electroplating bar, so that it can be incidentally cut away while singulating individual TFBGA package units.
In the case of QFN, a leadframe predefined with matrix of package sites (hereinafter referred to as “matrix leadframe”) is used for the fabrication of a batch of QFN package units. The QFN matrix substrate is typically formed with a grid-like connect bar along the borderlines of the package sites, for the purpose of connecting the inner leads of the leadframe together before being singulated. The final singulation process is typically performed by cutting into the provisional connect bar, so that it can be incidentally cut away while singulating individual QFN package units.
One problem in the singulation of TFBGA and QFN package units, however, is that, if the cutting is misaligned, it would undesirably leave remnant portions of the provisional electroplating bars or connect bars in the singulated package units, thus resulting in short-circuiting between the electrically-conductive traces (in the case of TFBGA) or inner leads (in the case of QFN), which would make the enclosed semiconductor chips inoperable. As a result, the finished package units will be regarded as defective ones. This problem is illustrated depicted in the following with reference to
FIGS. 1A-1E
for TFBGA and
FIGS. 2A-2E
for QFN.
Conventional TFBGA Singulation (
FIGS. 1A-1E
)
FIG. 1A
shows a schematic plan view of a TFBGA matrix substrate
100
used for TFBGA fabrication; and
FIG. 1B
shows a schematic sectional view of an unsingulated batch of TFBGA package units constructed on the TFBGA matrix substrate
100
(note that
FIGS. 1A-1B
are simplified to show only a small number of circuit components for demonstrative purpose; the actual circuit layout may be much more complex.)
As shown in
FIG. 1A
, the TFBGA matrix substrate
100
is predefined with a matrix of package sites
110
(only two are fully shown in
FIG. 1A
) used for the fabrication of a batch of TFBGA package units thereon. The package sites
110
are delimited from each other by a grid-like electroplating bar
120
which is formed along the borderlines of the package sites
110
, and are each formed with a plurality of electrically-conductive traces
130
on the front side thereof. To facilitate electroplating process, these electrically-conductive traces
130
are all connected to the electroplating bar
120
. Further, the package sites
110
are each mounted with at least one semiconductor chip
140
in the center of the front side thereof and electrically coupled to the electrically-conductive traces
130
.
Further, as shown in
FIG. 1B
, a continuous encapsulation body
150
is molded to encapsulate all the semiconductor chips
140
over the TFBGA matrix substrate
100
; and a plurality of solder balls
160
are implanted on the back side of the TFBGA matrix substrate
100
. The electrically-conductive traces
130
on the front side of the TFBGA matrix substrate
100
are connected through electrically-conductive plugs (not shown) to the solder balls
160
on the back side of the same, for the purpose of electrically connecting the semiconductor chips
140
to the solder balls
160
.
Before mounting the semiconductor chips
140
, it is required to perform an electroplating process so as to electroplate an electrically-conductive material, such as nickel-gold (Ni-Au), onto the electrically-conductive traces
130
. During the electroplating process, the electroplating electrical current is applied to the electroplating bar
120
, so that the electrical current can be then concurrently distributed by the electroplating bar
120
to each of the electrically-conductive traces
130
. After the electroplating process is completed, the electroplating bar
120
becomes a useless structure; and therefore, it can be subsequently cut away during the singulation process.
During the singulation process, a cutting blade
170
of a fixed width W greater than the width of the electroplating bar
120
is used to cut into the TFBGA matrix substrate
100
and the encapsulation body
150
along the crosswise singulation lines SL
X
and lengthwise singulation lines SL
Y
shown as dotted lines in
FIGS. 1A-1B
, for the purpose of singulating the combined batch of TFBGA package units constructed together on the TFBGA matrix substrate
100
into individual ones. The crosswise and lengthwise singulation lines SL
X
, SL
Y
should be precisely aligned to cover the entire width of the electroplating bar
120
within the cutting range of the cutting blade
170
.
As further shown in
FIG. 1C
, the cutting by the cutting blade
170
is carried out all the way into the TFBGA matrix substrate
100
and the encapsulation body
150
along the crosswise and lengthwise singulation lines SL
X
, SL
Y
. Through this singulation process, the combined batch of TFBGA package units are singulated into individual ones.
One drawback to the forgoing TFBGA singulation, however, is that, since the TFBGA matrix substrate
100
is typically very small in size, where the electroplating bar
120
is typically from 0.05 mm to 0.1 mm (millimeter) in width, typically 0.07 mm, and the cutting blade
170
used in the singulation process is typically 0.3 mm in width, In this case, the cutting tolerance is only (0.3-0.07)2=0.115 mm. In other words, the cutting blade
170
should be highly precisely aligned to the electroplating bar
120
along the crosswise and lengthwise singulation lines SL
X
, SL
Y
shown in
FIGS. 1A-1B
; otherwise, if the misalignment exceeds 0.115 mm, it would cause the problem of trace short-circuits.
As shown in
FIG. 1D
, in the event that the cutting blade
170
is misaligned with respect to a lengthwise portion of the electroplating bar
120
, then an edge part
1230
a
of the electroplating bar
120
will be uncovered by the lengthwise singulation lines SL
Y
. As a result, the uncovered edge part
120
a
of the electroplating bar
120
is beyond the cutting range of the cutting blade
170
.
As further shown in
FIG. 1E
, the case of
FIG. 1D
would cause the uncovered edge part
120
a
of the original electroplating bar
120
to remain over the edge of the singulated package site
110
, thus undesirably causing the electrically-conductive traces
130
to be short-circuited to each other. As a result, this singulated TFBGA package unit would be regarded as defective.
One solution to the foregoing problem is to use a cutting blade of a greater width to perf

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of singulating a batch of integrated circuit package... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of singulating a batch of integrated circuit package..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of singulating a batch of integrated circuit package... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2481404

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.