Method of simultaneously forming a line interconnect and a...

Details Method of simultaneously forming a line interconnect and a... Method of simultaneously forming a line interconnect and a...

2000-01-12

2001-06-12

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

Reexamination Certificate

active

06245651

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor processing and more specifically to front end of line (FEOL) methods for defining interconnects.
BACKGROUND OF THE INVENTION
Heretofore, in memory devices, especially DRAMs (dynamic random access memories) and logic chips having embedded DRAMs (eDRAMs), the process of fabricating bitline contacts to diffusion (CB contacts) has required lithography using a critical mask. Fabricating the bitlines themselves has required lithography using another critical mask. Critical mask lithography is expensive and error-prone due to attendant optical and alignment factors. Therefore, it would be desirable to simultaneously fabricate bitlines and bitline contacts to diffusion using the same critical mask. In the description of the invention that follows, those skilled in the art will recognize that bitlines are a specific example of a line interconnect, and bitline contacts are a specific example of contacts to diffusion.
Many semiconductor chips have array regions and support regions. The array regions may include densely packed devices that form a memory array for a DRAM or an eDRAM, while the support regions include less densely packed devices, typically logic, which may be optimized for speed, performance or power conservation. The different design goals for the array region and the support region require that different processing be applied to the respective regions. However, to reduce the cost of manufacturing such chips, it is desirable to combine the processing for both the array and the support regions, when certain steps can be performed which advance the design goals for both regions.
Accordingly, it is an object of the invention to provide a method of simultaneously defining line interconnects, e.g. bitlines, and contacts to diffusion, e.g. bitline contacts.
Another object of the invention is to provide a method of defining line interconnects and contacts to diffusion while requiring only one critical mask.
Still another object of the invention is to provide a method of simultaneously defining line interconnects, e.g. bitlines, array contacts to diffusion, e.g. bitline contacts, and support contacts to diffusion.
SUMMARY OF THE INVENTION
These and other objects are provided by the method of the present invention of simultaneously defining a line interconnect and borderless contacts to diffusion coincident thereto.
A semiconductor substrate having prepatterned gate stacks thereon is covered with a first dielectric to form a first level and then a second dielectric is deposited thereon which forms a second level. Line interconnect openings are defined in the second level by lithography and etching. Etching is continued down to monocrystalline regions in an array region of the substrate to form borderless contact to diffusion openings between the gate stacks which are coincident to the line interconnect openings. The openings are then filled with one or more conductors, preferably with polysilicon in the lower borderless openings, and preferably with a metal in the line interconnect openings above.
Preferably, the method herein is carried out simultaneously with respect to fabricating line interconnects and contacts to support (CS) in a support region of the substrate. The method begins with a semiconductor substrate having prepatterned gate stacks thereon which are covered with a first dielectric to form a first level. An etch stop layer is then formed over the first level in the support region but not in the array region. A second dielectric (MO level) layer is deposited over both array and support regions. Line interconnect openings are then made in both array and support regions. Etching is continued, selective to the etch stop layer, thereby forming borderless contact to diffusion openings between the gate stacks in the array region while leaving the first level in the support region intact.
The etch stop layer is then removed from the support region. A contact to diffusion conductor, preferably polysilicon, is deposited in the lower borderless openings and then removed from the line interconnect openings above. Alternatively, ion implantation can be performed at this point, allowing the polysilicon deposition and etchback to be skipped.
Then, in the support region, contacts to diffusion openings are defined and etched coincident to the line interconnects. Finally, a metal, such as tungsten, is then deposited to fill the openings, thereby forming array contacts to diffusion (e.g. bitline contacts), if not already formed by a prior polysilicon deposition, and line interconnects (e.g. bitlines) in the array region. The metal deposition simultaneously forms the support contacts to diffusion (CS) and line interconnects in a support region (e.g. as logic interconnects).


REFERENCES:
patent: 5792703 (1998-08-01), Bronner et al.
patent: 5899742 (1999-05-01), Sun

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