Method of simultaneously displaying schematic and timing data

Details Method of simultaneously displaying schematic and timing data Method of simultaneously displaying schematic and timing data

2001-08-03

2003-05-13

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06564365

ABSTRACT:

FIELD OF INVENTION
The present invention relates generally to integrated circuit design. More particularly, it relates to the display of circuit information in a schematic format.
BACKGROUND
In the field of integrated circuit (IC) design and particularly very large scale integration (VLSI) design, circuits are stored as data in a computer memory and manipulated or tested using an electronic computer-aided design (E-CAD) software tool. As used herein, E-CAD tool is meant in the broadest sense and refers to any application for analyzing a circuit design. It may include one or more separate applications for analyzing specific aspects of the design. The memory may store an archive file containing display information for the circuit. Based on this information, the E-CAD tool may create a visual display of the circuit, or a portion of the circuit, in a schematic format.
A circuit may contain multiple elements, such as logic gates and state elements, as well as connections between the elements. Each signal carried between elements may be individually named for analysis. The netlist may be a data file that stores signal names along with the connection information. Methods are known for displaying the signal names on the schematic display by retrieving this information from the netlist. This may be performed, for example, using a schematic drawing application, which may be part of the E-CAD tool or may be a separate application.
In circuit design, substantial time is often required to resolve timing problems for the signals. This is particularly the case in long timing paths found in VLSI designs. For example, a circuit design specification may have minimum and maximum times (min-time, max-time) for signals to travel from one state element, such as a latch, to another state element. If the path timing breaks the min-time specification, it may “race” through the next state element by arriving before a clock that controls the next state element. If the path timing breaks the max-time specification, it may arrive at the next state element during an incorrect clock state. For this reason and others, it is desirable to know the timing for each signal in a circuit or portion thereof.
Timing information is typically retrieved using a timing analyzer software application. The timing analyzer may be part of the E-CAD tool, or it may be a separate application. The timing analyzer is run on each path in the circuit, or portion thereof under test, to identify paths that do not comply with the specification. Once a slow or fast path is identified, the designer may examine each of the signals in the path to identify the problem signal(s). The designer then attempts to resolve the problems in the identified paths by changing gates or by completely redesigning the logic. The timing analyzer is then re-run on the redesigned circuit. In order to resolve a design violation, the designer may have to slow down or speed up certain paths by slowing down or speeding up certain signals. Because some signals may pass to other parts of the design, other than the problematic path under test, the process of changing signal speeds in a design can become difficult. Existing timing analyzers produce a list of timing information for all signals under test or a list of problem paths comprising one or more signals. This is cumbersome to analyze because the designer must correlate this raw data with the raw connection data from the netlist, or with a schematic diagram produced from the netlist, in order to analyze timing problems. This is particularly difficult when the designer attempts to change the timing of signals. What is needed is a more convenient way of displaying timing and other circuit information to assist a designer in resolving problems in circuit paths.
SUMMARY OF INVENTION
A method is disclosed for more conveniently displaying circuit information in a schematic format by creating a visual representation of information about particular signals as part of a schematic representation of the signals. The method applies to a circuit design stored as data in a computer memory, which design may be displayed as a schematic using x-y coordinates for wires, circuit elements, instance names, and signal names. Signal names are retrieved from the circuit design. Display coordinates for the signal names are retrieved from the circuit design. Signal information, such as timing information for the signals, is retrieved for example from a timing analyzer. Using the x-y coordinates, the signal information is displayed as part of the schematic. The information may be displayed by overlaying or backgrounding the signal information over an existing schematic display or a single schematic display file may include the signal information, for example by appending this information to an existing archive file, which contains the instructions for building the original schematic.
A method is also disclosed for designing a circuit by displaying signal information on a schematic diagram of the circuit to aid in resolving design problems. A circuit design is stored as data in a computer memory. An E-CAD tool software application is performed on the design to create an archive file containing x-y display coordinates for displaying the signals as part of a schematic. The archive file contains names and locations of all signals. The design is analyzed to extract signal information. For example timing information may be extracted using a timing analyzer. The information is stored in a data file, such as a timing data file in the computer memory. Timing information and signal display coordinate information may be combined into a new archive file that is used to create a schematic diagram of the circuit, or a portion of the circuit, in which the timing information is displayed near the signals and signal names. Based on the displayed timing information, the designer can identify and attempt to resolve problem signals in the design. The process can then be repeated by re-running the analysis tool on the modified design to determine whether the design meets specifications.
A computer-readable medium is also disclosed having computer executable instructions for displaying signal timing information on a circuit schematic. The instructions retrieve signal names and x-y coordinates for the signals or the names from a circuit design stored in a memory. The instructions then receive timing or other signal information from a timing analyzer or other such signal information extractor. Using the x-y coordinates for the signals or the signal names, the instructions display the signal information on a schematic diagram of the circuit, or part thereof.


REFERENCES:
patent: 5867399 (1999-02-01), Rostoker et al.
patent: 5880971 (1999-03-01), Dangelo et al.
patent: 5903469 (1999-05-01), Ho
patent: 2002/0046015 (2002-04-01), Croix

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