Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Recessed oxide by localized oxidation
Reexamination Certificate
1999-06-16
2001-05-29
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Recessed oxide by localized oxidation
C438S225000, C438S297000, C438S362000, C438S410000
Reexamination Certificate
active
06239003
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of electronic devices and more particularly to a semiconductor device having simultaneously fabricated isolation and gate regions and a method for fabricating the same.
BACKGROUND OF THE INVENTION
Local oxidation of silicon (LOCOS) has become a popular method of fabricating semiconductor devices. LOCOS typically involves forming isolating dielectric regions between active regions of devices, to electrically isolate each device sharing a common substrate. These isolating dielectric regions are typically formed by thermally growing oxide between stacks of nitride on silicon oxide disposed over areas that will become active regions of the substrate. Using conventional LOCOS techniques, the thermally grown isolating oxide generally tends to encroach into the active regions of the substrate, limiting the packing density of semiconductor devices in the resulting structure.
One approach to reducing the encroachment of the isolation dielectric into the active regions of the substrate is to form a thick nitride shield over a pad oxide, which is disposed on the substrate. A problem with this approach, however, is that the presence of the thick nitride shield stresses the silicon in the active region during formation of the isolation dielectric which creates stress related imperfections, such as dislocations, in the silicon. An additional problem with this approach is that the resulting structure exhibits a non-planar surface, which makes focusing lithography equipment difficult.
Another approach to protecting the substrate from these stresses is commonly referred to as poly-buffered LOCOS (PBL). This approach involves forming a disposable polysilicon buffer layer between the pad oxide and the nitride shield to absorb stresses from the nitride on the substrate. Although the polysilicon buffer layer acts to absorb some stress, this approach still suffers from difficulties in lithography created by the resultant nonplanar surfaces. Still another approach, referred to as sidewall-sealed poly-buffered LOCOS (SSPBL) is similar to PBL, with the added features of etching a trench into the silicon and implementing sidewall protective structures in an effort to limit encroachment of the isolation oxide and maintain a planar surface. Each of these approaches has a disadvantage of using a disposable polysilicon buffer structure, which must later be replaced with another silicon structure to form a gate, resulting in additional fabrication time and expense.
SUMMARY OF THE INVENTION
In accordance with the teachings of the present invention, a method of forming a semiconductor device is provided that substantially eliminates or reduces the disadvantages associated with prior techniques and processes.
In accordance with one embodiment of the present invention, a method of forming a semiconductor device comprises forming a moat stack outwardly from a substrate, the moat stack comprising a dielectric pad disposed outwardly from the substrate, a silicon buffer structure disposed outwardly from the dielectric pad, and a protective dielectric cap disposed outwardly from the silicon buffer structure. The method further comprises forming a protective sidewall structure outwardly from at least a sidewall of the silicon buffer structure, forming an isolation dielectric region adjacent to the moat stack, after formation of the isolation dielectric region removing the protective dielectric cap, and forming a conductive gate comprising the silicon buffer structure.
Technical advantages of the present invention include the provision of a method of fabricating a semiconductor device in which a silicon buffer structure used to shield an active region of the substrate from stress during fabrication can be reused as a conductive gate in a variety of semiconductor devices. The invention saves time and expense in the fabrication process by eliminating the need to remove and discard the silicon buffer structure only to replace it with another silicon gate structure.
In addition, through the use of substantially amorphous silicon in the silicon buffer structure, the invention more effectively reduces stress on the silicon of the active regions of the substrate during formation of isolation dielectric regions. Using amorphous silicon in silicon buffer structure further provides an advantage of being resistant to stresses during fabrication, resulting in an effective and reliable gate. Undercutting the silicon buffer structure helps to relieve stress on the active region of the substrate, by eliminating a source of stress transmission from the protective dielectric cap. The undercut regions of the silicon buffer structure also provide an effective anchor for the protective sidewall structures used during the fabrication process.
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Avid Kanger, et al.,An Integrated Isolation/Gate Process for Sub-Quarter Micron Technologies,AT&T Bell Laboratories, 11-3, pp. 141-142.
Chen Kueing-Long
Guldi Richard L.
Rao Kalipatnam V.
Blum David S.
Bowers Charles
Brady III W. James
Garner Jacqueline J.
Telecky , Jr. Frederick J.
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