Method of silicon oxide and silicon glass films deposition

Details Method of silicon oxide and silicon glass films deposition Method of silicon oxide and silicon glass films deposition

1999-03-18

2001-03-06

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S778000, C438S788000, C438S790000

Reexamination Certificate

active

06197705

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of a silicon oxide and silicon glass deposition using a combined power-optimized Plasma-Activated CVD with tetraethoxysilane-ozone-oxygen reaction gas mixture (TEOS-O
3
/O
2
PACVD).
2. Description of the Prior Art
In the fabrication of devices such as semiconductor devices, a variety of material layers is sequentially formed and processed on the substrate. (For the purpose of this disclosure, the substrate includes a bulk material such as semiconductor, e.g., silicon, body, and if present, various regions of materials such as dielectric materials, conducting materials, metallic materials, and/or semiconductor materials). Often, one of the material regions utilized in this fabrication procedure includes a silicon oxide, i.e., a material nominally represented by the formula SiO
n
, where n=~2. For example, silicon oxide regions are utilized as insulating/passivating layers as electrical insulation between conducting layers, e.g., polysilicon or metal layers, and as a cap doped semiconductor layers to limit unacceptable dopant migration during subsequent processing.
A silicon oxide is often deposited on a non-planar substrate having a plurality of steps, e.g., conducting steps. Substrate represents a semiconductor structure
10
and overlying layers (e.g., lines
112
). It is desirable that the deposited silicon oxide conformally coats this non-planar surface. If a conformal silicon oxide layer is not achieved, an irregular coating, (
118
in FIG.
1
), forms over the underlying steps,
112
. If deposition is continued, voids,
110
, as shown in
FIG. 2
, are often produced. An irregular coating such as shown in
FIG. 1
is, in many situations, unacceptable because a non-planar surface degrades the resolution of subsequent photolithography. Voids such as shown in
FIG. 2
are even less desirable because etching and dielectric properties will be non-uniform. In either case, lack of planarity generally produces difficulties in subsequent processing. Therefore, it is very desirable to produce a conformal coating.
The prior art processes do not provide conformal oxide layer that can conformally cover on and between the increasingly tight step features of new semiconductor devices without forming seams.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following:
U.S. Pat. No. 5,593,741 (Ikeda) Method and apparatus for forming silicon oxide film by chemical vapor deposition—shows oxide and oxynitride film Plasma-Enhanced Chemical Vapor Deposition methods in parallel plate reactor type (PECVD), or electron cyclotron resonance type (ECR) reactor with about 1 second cycled-plasma excitation of the gas mixture to provide cycled concentration of the high degree ionized molecules.
U.S. Pat. No. 5,271,972 (Kwok) Method for depositing ozone/TEOS silicon oxide films of reduced surface sensitivity—teaches a method of depositing good quality thermal CVD silicon oxide layers over a PECVD TEOS/oxygen silicon oxide layer comprising forming an interstitial layer by ramping down the power in the last few seconds of the PECVD deposition. This invention has a step with the lowering of the plasma power of PECVD film deposition that helps to reduce the surface sensitivities of the following TEOS-ozone SACVD oxide.
U.S. Pat. No. 5,643,839 (Dean) Low temperature deposition of silicon oxides for device fabrication—teaches a deposition process involving a plasma struck in a gas including tetraethoxysilane and source of oxygen yields, at low temperatures, conformal coatings of silicon dioxide.
U.S. Pat. No. 5,362,526 (Wang) Plasma-Enhanced CVD process using TEOS for depositing silicon dioxide—teaches a multi-step deposition process. The CVD SiO2 process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer is described. Various combinations of the steps are disclosed for different applications.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a silicon oxide layer that combines advantages of both low temperature Plasma-Enhanced Chemical Vapor Deposition (PECVD) and low temperature Sub-Atmospheric Chemical Vapor Deposition (SACVD) using power-optimized Plasma-Activated CVD with TEOS-ozone-oxygen reaction gas mixture (TEOS-O
3
/O
2
PACVD).
It is an object of the present invention to provide a method for fabricating a silicon oxide layer over a stepped surface using power-optimized Plasma-Activated CVD with TEOS-ozone/oxygen reaction gas mixture that produces in oxide layer with rounded comers, not sharp corner or flow-like corners with good integrity of film along the device steps.
The invention shows a soft power-optimized Plasma-Activated CVD with of TEOS-O
3
/O
2
reaction gas mixture. The invention combines the advantages of both low temperature PECVD and SACVD methods. The invention disclosures a process to deposit silicon oxide by a process TEOS O
3
/O
2
PACVD that uses TEOS and O
3
/O
2
gas mixture and soft power-optimized reaction conditions.
A preferred process TEOS-O
3
/O
2
PACVD is shown below in Table 1:
TABLE 1
Inventions “soft plasma
activation” of TEOS-O
3
/O
2
-
(dopants) gas mixtures -
example of
Estimated range of
preferred set
Process Parameter
parameters
of parameters
wafer temperature (C.)
300-600
450 (425-475)
pressure (torr)
0.2-20
9.5
RF frequency (KHz)
400-1356
1350
plasma density (W/cm
−2
)
0.05-0.5
0.2
ozone concentration in
0.5-15
11.8
(O
3
/O
2
) mixture (wt %))
Total oxidizer flow rate
1000-8000
5000
(O
3
+ O
2
) (sccm)
TEOS flow (mgm)
100-1000
400
He flow (sccm)
1000-6000
2000
Wafer spacing (mls)
200-600
250
The most critical parameters in the invention are RF plasma density, ozone concentration in oxygen and the deposition temperature.
The invention has the following advantages: stationery CVD process; no surface sensitivity; improvement of step coverage; comer rounding and improvement of film integrity in the bottom corners of structures; power can be used as an addition parameter for management of dopant oxide deposition—simply realized; no need to change chamber design.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by the reference to the latter portions of the specification and attached drawings.


REFERENCES:
patent: 5271972 (1993-12-01), Kwok et al.
patent: 5362526 (1994-11-01), Wang et al.
patent: 5593741 (1997-01-01), Ikeda
patent: 5643838 (1997-07-01), Dean et al.
patent: 5933760 (1999-08-01), Iyer et al.
patent: 4-38829 (1992-02-01), None
“The Electric Properties of CVD Silicon Oxide Films for Applications as Interlayer Dielectrics in USLI”, 1997 IEEE Annual Report, Loiko et al., Conference on Electrical Insulation and Dielectric Phenomena, Oct. 10-22, 1997.

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