Method of shared intervention via a single data provider among s

Details Method of shared intervention via a single data provider among s Method of shared intervention via a single data provider among s

1997-04-14

1999-08-24

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711144, 711145, 711143, G06F 1200

Patent

active

059436859

ABSTRACT:
A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. A requesting processing unit issues a message to an interconnect of the computer system indicating that the requesting processing unit desires to read a value from an address of a memory device of the computer system, and each cache snoops the interconnect to detect the message. Each cache thereafter transmits a response to the message, the response selected from the group consisting of an invalid response, a modified intervention response, a shared intervention response, or an alternative response, wherein the invalid response indicates that a cache does not contain any value corresponding to the address of the memory device, the modified intervention response indicates that a cache contains and can source a modified value corresponding to the address of the memory device, and the shared intervention response indicates that a cache contains and can source an unmodified value corresponding to the address of the memory device. A priority can be associated with each response from each cache, and the responses detected by system logic, the system logic forwarding a selected one of the responses to the requesting processing unit based on the highest priority response. Since the cache latency can be much less than the memory latency, the read performance can be substantially improved with this new protocol.

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