Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-02-20
2007-02-20
Whitmore, Stacy A. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C382S144000, C382S145000
Reexamination Certificate
active
10385628
ABSTRACT:
Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit, predicting a third pattern by using the process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer in an etching process, obtaining an evaluation value by comparing the third pattern with the first pattern, determining whether the evaluation value satisfies a preset condition, and changing the process parameter information when the evaluation value is found not to satisfy the preset condition.
REFERENCES:
patent: 5225998 (1993-07-01), Singhal
patent: 6161054 (2000-12-01), Rosenthal et al.
patent: 6368884 (2002-04-01), Goodwin et al.
patent: 6470230 (2002-10-01), Toprac et al.
patent: 6577994 (2003-06-01), Tsukuda
patent: 6587744 (2003-07-01), Stoddard et al.
patent: 6622059 (2003-09-01), Toprac et al.
patent: 6633831 (2003-10-01), Nikoonahad et al.
patent: 2002/0002697 (2002-01-01), Kotani et al.
patent: 2002/0026626 (2002-02-01), Randall et al.
patent: 2002/0078427 (2002-06-01), Palmer et al.
patent: 2002/0091986 (2002-07-01), Ferguson et al.
patent: 2002/0188417 (2002-12-01), Levy et al.
patent: 2003/0046653 (2003-03-01), Liu
patent: 2004/0044431 (2004-03-01), Pellegrini et al.
patent: 2005/0193361 (2005-09-01), Vitanov et al.
patent: 7-175204 (1995-07-01), None
patent: 2000-277426 (2000-10-01), None
patent: 2001-14376 (2001-01-01), None
patent: 2002-26126 (2002-01-01), None
Notification of Reasons for Rejection issued by Japanese Patent Office mailed Apr. 18, 2006, in Japanese Application No. 2003-064592 and English translation of Notice.
Kokai, Jan. 25, 2002, Japnese Publication Translation from Japan Patent Office website. pp. 1-5.
Hashimoto Koji
Inoue Soichi
Kotani Toshiya
Mori Ichiro
Tanaka Satoshi
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Whitmore Stacy A.
LandOfFree
Method of setting process parameter and method of setting... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of setting process parameter and method of setting..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of setting process parameter and method of setting... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3883114