Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-10-10
2006-10-10
Whitmore, Stacy A. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07120882
ABSTRACT:
Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit, predicting a third pattern by using the process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer in an etching process, obtaining an evaluation value by comparing the third pattern with the first pattern, determining whether the evaluation value satisfies a preset condition, and changing the process parameter information when the evaluation value is found not to satisfy the preset condition.
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Notification of Reasons for Rejection issued by Japanese Patent Office mailed Apr. 18, 2006, in Japanese Application No. 2003-064592 and English translation of Notice.
Hashimoto Koji
Inoue Soichi
Kotani Toshiya
Mori Ichiro
Tanaka Satoshi
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Whitmore Stacy A.
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