Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2006-10-23
2008-11-04
Ramos-Feliciano, Eliseo (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S064000, C702S118000, C702S119000, C324S765010
Reexamination Certificate
active
07447606
ABSTRACT:
A IC wafer is fabricated using a process of interest to have a plurality of FET devices with different channel lengths (Leff) form a plurality of channel length groups. The threshold voltage (VT) is measured of a statistical sample of the FET devices in each channel length group at two different drain-to-source voltage (VDS). The mean of VT is calculated for each channel length and each VDS. A slope coefficient λ relating VT to Leff is calculated at each VDS. The total variance of VT is calculated at each VDS. Two equations at each VDS, each relating the total variance of VT to the variance of VT with respect to dopant levels and the square of the slope coefficient λ times the variance of Leff, are solved simultaneously to obtain the variance of VT with respect to dopant levels and the variance of Leff.
REFERENCES:
patent: 5438527 (1995-08-01), Feldbaumer et al.
patent: 2002/0063572 (2002-05-01), Yamaguchi et al.
patent: 2005/0193013 (2005-09-01), Yamashita et al.
Agarwal Kanak B.
Nassif Sani R.
Huynh Phuong
International Business Machines - Corporation
Ramos-Feliciano Eliseo
Salys Casimer K.
Winstead P.C.
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