Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output process timing
Reexamination Certificate
2000-04-06
2003-03-18
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output process timing
C710S004000, C710S007000, C710S020000, C710S021000, C710S032000, C710S035000, C710S052000, C710S058000, C710S053000, C710S056000, C710S065000, C710S310000
Reexamination Certificate
active
06535935
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to methods of sending multiple streams of data from a memory thru a controller to respective I/O devices, where a) the controller is coupled to the I/O devices thru at least one external data buffer (such as a data buffer in a bridge), and b) each stream of data is sent via a transmission burst in which the receipt of individual data words are not acknowledged.
One particular use for the present invention is to aid in the execution of multiple WRITE-TO-DISK instructions. With each WRITE-TO-DISK instruction, a stream of data is read from a memory by a controller; and concurrently, the controller sends the data to the particular disk on which the data is to be written. Typically, the stream of data is in the form of a data chain which consists of several data blocks that have separate starting addresses in the memory and are linked together by a list of pointers.
In the simplest case, the controller is coupled by a single I/O bus directly to a bus adapter for a set of disks. However, only a limited number of bus adapters, with their respective disks, can be attached to a single I/O bus. Thus, one or more bridges are often coupled between the controller and the bus adapters, in order to increase the total number of disks above the limit for the single bus.
Usually a bridge includes a data buffer which temporarily holds a portion of the data stream that is sent thru the bridge. But due to that data buffer, a problem arises when the data stream is sent thru the bridge via a transmission burst to a bus adapter which is of a type that can stop the transmission burst at any time by sending a terminate signal.
When such a terminate signal is sent, a portion of the data stream will be in the data buffer of the bridge, where it will be discarded. Thus the controller is unable to determine how much data was actually received by the bus adapter; and consequently, the controller is unable to restart the execution of the WRITE-TO-DISK instruction at the point where the terminate signal occurred.
One method for dealing with the above terminate problem is to send the data stream from the controller thru the bridge to the bus adapter such that a separate acknowledgment signal is sent by the bus adapter for each word of data that it receives. However, when the data is sent by that method, the transmission rate is greatly reduced in comparison to the burst mode of transmission wherein separate acknowledgment signals for each received data word do not occur.
Another method for dealing with the above terminate problem is to receive from the bus adapter, at some time after the terminate signal, the address in the memory of the last word which the bus adapter actually received. Then, the controller can restart the execution of the WRITE-TO-DISK instruction by re-reading the data stream from the memory starting at the received address; and by concurrently sending the data which it reads to the bus adapter.
However, the above method is also slow because it requires portions of the data stream to be re-read by the controller from the memory before the transmission burst to the bus adapter can be re-started. Further, the above method does not even work in the case where the data stream is in the form of a data chain because the controller cannot detect when the data in the stream that it receives during a transmission burst, changes from one data block in the memory to another data block.
Accordingly, a primary object of the present invention is to provide a method of sending streams of data from a memory thru a controller and an external data buffer to I/
0
devices, via a transmission bursts, in which the above problems are overcome.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, a stream of data words is sent from a memory thru a controller and an external data buffer to an I/O device by a method which includes the following five steps:
1) transferring a segment of the stream of data from the memory into the controller while concurrently sending a subsegment of the segment from the controller thru the data buffer to the I/O device via a transmission burst in which the receipt of individual parts of the subsegment are not acknowledged by the I/O device;
2) receiving a signal in the controller, from the I/O device at any time during the sending step, to terminate the transmission burst;
3) subsequently receiving a signal in the controller, from the I/O device, to restart the transmission burst beginning with a selectable part of the last subsegment that was sent;
4) removing from the controller, only the portion of the segment which precedes the selectable part of the subsegment; and,
5) repeating the above steps until the stream of data is received in its entirety by the I/O device.
With the above method, each part of the entire data stream is read from the memory and transferred into the controller only one time. This occurs due to the step in the above paragraph 4). By comparison, selectable parts of the data stream subsegments are sent twice from the controller thru the external data buffer to the I/O device. This occurs due to the step in the above paragraph 3).
To perform the above method, the controller preferably includes a novel refetchable first-in-first-out memory (RFIFO). In operation, the controller writes each segment of the data stream into the RFIFO in a first cyclic sequence, and the controller reads each subsegment from the RFIFO in a second sequence. This second sequence is the same as the first sequence except that the second sequence backs-up in response to the signal to restart the transmission burst beginning with a selectable part of the subsegment. Such reading of the RFIFO in the second sequence, which backs-up, cannot be accomplished by a conventional first-in-first-out memory because a conventional first-in-first-out memory can only be read in a single fixed cycle.
REFERENCES:
patent: 5917503 (1999-06-01), Zakharia et al.
patent: 6108723 (2000-08-01), Simms et al.
patent: 6243768 (2001-06-01), Khandekar
Carlson Lewis Rossland
Carver, II John James
Farooq Mohammad O.
Fassbender Charles J.
Gaffin Jeffrey
Rode Lise A.
Starr Mark T.
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