Method of semiconductor wafer testing

Details Method of semiconductor wafer testing Method of semiconductor wafer testing

1998-03-10

2000-01-11

Bowers, Charles

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

438 23, H01L 2102, H01L 2166

Patent

active

060135379

ABSTRACT:
The present invention is a structure and method to reduce the inductance of the AC test signal path used for testing an electrical device contained within a semiconductor wafer. This extends the frequency range of testing. It enables testing the devices perform characteristics at higher frequencies than otherwise useable. It is particularly directed for testing on-wafer VCSELs. The method provides to the electrical device the characteristics of a microwave bias-tee device. An on wafer capacitor is designed into the environment of the electrical device enabling the formation and use of the three ports of a bias-tee. Preferably, the bias-tee is formed in a manner not requiring the addition of processing steps to the wafer manufacturing process. The method further provides a way to increase the capacitance of the on-wafer capacitor.

REFERENCES:
patent: 5317587 (1994-05-01), Ackley et al.

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