Method of semiconductor manufacture using an inverse self-aligne

Details Method of semiconductor manufacture using an inverse self-aligne Method of semiconductor manufacture using an inverse self-aligne

1991-07-30

1992-07-21

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437228, 437984, 437978, 148DIG102, H01L 21265, H01L 21465

Patent

active

051322366

ABSTRACT:
A process for fabricating a CMOS integrated circuit having both P-channel and N-channel areas in the substrate. The process forms a single self-aligned mask to define the positions of both of the channel areas on the substrate. The process includes: depositing a maskable material on the substrate; photopatterning and etching the maskable material to expose a pattern of areas on the substrate; tailoring the pattern of areas as P-channel or N-channel; depositing a second material over the maskable material and over the tailored areas of the substrate; chemically mechanically polishing (CMP) the second material to an endpoint of the maskable material; selectively etching the maskable material to expose a second pattern of areas on the substrate aligned with the first pattern of areas; and then tailoring the second pattern of areas as P-channel or N-channel.

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