Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...
Reexamination Certificate
2000-03-29
2003-02-25
Butler, Dennis M. (Department: 2185)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
C712S200000
Reexamination Certificate
active
06526520
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of synchronization and reconfiguration of configurable elements in a programmable unit.
BACKGROUND INFORMATION
Synchronization of configurable elements in conventional units (e.g., FPGAs, DPGAs, etc.) is usually based on the clock pulse of the unit. This type of time-controlled synchronization poses many problems. One problem is that the amount of time a task will require is often not known until a final result is achieved. Another problem with time-controlled synchronization is that the event upon which the synchronization occurs is triggered by an independent element instead of the element to be synchronized itself. In this case, two different elements are involved in the synchronization which leads to high management overhead.
SUMMARY OF THE INVENTION
The present invention relates to a method for synchronization based on the elements to be synchronized themselves. In accordance to an exemplary embodiment according to the present invention, synchronization is no longer implemented or administered by a central instance. By making synchronization the responsibility of each element, more synchronization tasks can be performed at the same time because independent elements no longer interfere with each other in accessing the central synchronization instance.
In a unit with a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.), any configurable element can have access to the configuration and status register of the other configurable elements via an interconnection architecture and can thus have an active influence on their function and operation. Thus, in addition to the usual method, the configuration may also take place from a processing array (see PACT02: PA) through a primary logic unit.
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Münch Robert
Vorbach Martin
Butler Dennis M.
Kenyon & Kenyon
Pact GmbH
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