Method of selectively exposing the sidewalls of a trench and its

Details Method of selectively exposing the sidewalls of a trench and its Method of selectively exposing the sidewalls of a trench and its

1984-06-29

1985-10-29

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

29576W, 29580, 148187, 156646, 156648, 156649, 156653, 156657, 1566591, 156662, 204192EC, 204192E, 357 49, H01L 21306, B44C 122, C03C 1500, C23F 102

Patent

active

045499276

ABSTRACT:
Deep trenches (14,15) are formed according to the desired pattern through the N epitaxial layer (13) and N.sup.+ subcollector region (12) into the P.sup.- substrate (11) of a silicon structure (10). Where a substrate contact is needed, the trenches delineate a central stud (16) or mesa of silicon material. Channel stop regions (18) are formed e.g. by ion implantation of boron atoms at the bottom of trenches, SiO.sub.2 and Si.sub.3 N.sub.4 layers (17,19) are then deposited on the whole structure. A substrate contact mask is applied and patterned to selectively expose one side of the trench sidewalls, the bottom of the trenches adjacent thereto and others areas if desired such as the top surface of the stud. The composite SiO.sub.2 /Si.sub.3 N.sub.4 layer is then etched to leave exposed only the sidewalls of the stud, at least partially the bottom of the trenches adjacent thereto and the top surface of the stud. Platinum is deposited preferably via sputter deposition, conformally coating all regions of the structure. After sintering, the unreacted platinum is removed using wet chemical etch (aqua regia). Platinum silicide is left in all opened contacts and on the stud sidewalls where its defines a metal silicide lining (25) or cap, covering the stud. This lining connects the top surface (25a) of the stud, with the channel stop implanted regions (18) and then forms the desired substrate contact.

REFERENCES:
patent: 3381182 (1968-04-01), Thornton
patent: 4118728 (1978-10-01), Berry
patent: 4149177 (1979-04-01), Alter
patent: 4356622 (1982-11-01), Widmann
IBM Technical Disclosure Bulletin, vol. 25, No. 12, May 1983, "Simplified Isolation for an Integrated Circuit" by S. A. Abbas et al. pp. 6611-6614.
IBM Technical Disclosure Bulletin, vol. 25, No. 8, Jan. 1983, "Plasma-Oxide-Filled Deep Dielectric Isolation" by J. S. Basi et al. pp. 4405-4406.
IBM Technical Disclosure Bulletin, vol. 20, No. 11A, Apr. 1978, pp. 4445-4446.
IBM Technical Disclosure Bulletin, vol. 24, No. 12, May 1982, p. 6483.

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