Method of selecting and synthesizing metal interconnect...

Details Method of selecting and synthesizing metal interconnect... Method of selecting and synthesizing metal interconnect...

1998-01-14

2001-02-13

Teska, Kevin J. (Department: 2768)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06189131

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the synthesis and design of integrated circuits, and more particularly to assigning interconnect wires to specific metal layers through the use of interconnect wire load models that are metal layer dependent.
2. Description of the Related Art
Integrated circuits have become key components of many consumer and commercial electronic products, often replacing discrete components and enhancing product functionality. The semiconductor processing technologies that produce these integrated circuits have advanced to the point where complete systems can now be reduced to a single integrated circuit or application specific integrated circuit (ASIC) device. These integrated circuits (also referred to as “chips”) may incorporate many functions that previously could not be implemented together on a single chip, including: microprocessors, digital signal processors, mixed signal and analog functions, large blocks of memory and high speed interfaces. The requisite level of integration, however, significantly complicates the design and manufacturing processes.
One difficult task facing integrated circuit manufacturers is interconnecting the millions of logic gates and megabytes of memory that may be present on a chip. To aid in this task, new metallization schemes have been developed that allow five or more distinct “levels” or layers of metal interconnect wires, with pitches of 0.125 &mgr;m and tighter on the first few layers. Additionally, new planarization procedures such as chemical-mechanical polishing help to flatten the insulating oxide layers between the metal layers in order to provide an even surface for subsequent lithography steps. These techniques eliminate potential optical distortion that may occur when subsequent layer patterns are formed using photolithographic techniques, and allow finer dimensions to be created. In most multiple layer metallization schemes, the various metal interconnect wires have different nominal widths and heights, different distances from transistor gates, and are insulated by oxide layers of varying thickness.
As semiconductor processes migrate into the deep submicron range with multiple metal layers, increased circuit speeds allow the delay caused by the metal to reach the magnitude of active elements. The aforementioned differences in the physical properties of the metal layers cause different metal layers to exhibit somewhat dissimilar electrical characteristics, resulting in disparities in propagation delays that a signal experiences when communicated over routing wires formed from the different metal layers. Today's integrated circuit verification and synthesis tools do not adequately account for such differences, instead relying on generic wire delay models for all metal layers to estimate actual delays. The inherent inaccuracies of these generic models may result in a signal path that does not perform as expected.
When performing timing analysis on a typical integrated circuit design, synthesis and timing analysis tools initially estimate timing information using the generic wire delay values. To improve timing accuracy, post placement or layout timing information can be back-annotated to these EDA tools. Standard file formats, such as the standard delay format (SDF), the design exchange format (DEF), and the physical design exchange format (PDEF), are used to pass data between floorplanning and the synthesis environment for interconnect delay modeling. This information improves the accuracy of delay values by providing the actual length of metal interconnect wires. In the interest of improving manufacturing yields, functional simulations can then be performed using these estimated delay values. Modifications to the layout database may be required to correct any detected problems. The terms “floorplan” and “layout” refer to the physical geometry of an integrated circuit or die. A floorplan consists of placed groupings of integrated circuit elements that are used by signal wire routing tools in placing and functionally interconnecting the elements. A layout includes the completed integrated circuit design and is represented by a layout database containing information for generating the masks used to fabricate integrated circuits.
The shortcomings in today's wire models can be significant given the larger areas (and corresponding increases in interconnect lengths) typically required by integrated circuits. Often, the performance of the integrated circuitry can be dominated by propagation delays through longer metal interconnect wires rather than the basic gate delays of individual logic elements. This phenomenon is exacerbated by the fact that as the width of a wire shrinks in deep submicron designs, the resistance of the wire increases. It has been estimated that interconnect thus determines as much as 70-80% of the total delay in integrated circuits implemented in 0.25 &mgr;m process rules. An increase in average propagation delays may result in a greater number of critical timing paths (e.g., signal paths in which best or worst case simulated propagation delays may approach the limits required for proper functionality). Many timing problems involve such critical timing paths.
Despite the use of sophisticated EDA tools, timing paths or “nets” do not always perform as expected when the completed integrated circuit is tested. Propagation delays through critical paths sometimes vary from simulated values for any of a number of reasons, most frequently due to mismatches between wire delay models and actual delays. Even when fairly accurate delay models are available to perform post layout timing analysis, there is currently no satisfactory method for incorporating these models into earlier stages of the design flow to reduce costly iterations between synthesis and layout steps to correct timing violations.
SUMMARY OF THE INVENTION
Briefly, the present invention provides a method for using layer specific wire load models in the synthesis and layout of integrated circuits. The method allows synthesis and layout tools to route signal wires on select metal layers at an early stage in the design process.
In a method according to the invention, a technology library for use in designing integrated circuits is provided. In addition to traditional library components such as logic gate information, the technology library includes routing wire load models that are metal layer dependent. The wire load information reflects the electrical properties of signal wires formed on different metal layers, and provides more accurate timing estimates than generic wire delay values.
The multi-layer wire load models supplied to the synthesis tool are used to assign individual signals to a specific metal layer(s). The additional information influences the delay calculations of the synthesis process in such a way that more accurate delay values are calculated, and the delay that a signal encounters on a specific metal layer can be approximated very closely. Of significance to the present invention, a wire-metal layer attribute file is compiled by the synthesis process. The wire-metal layer attribute file output directs layout tools to route individual signals on specific metal layers. Alternatively, the layout tool can utilize the wire-metal layer attribute file to determine a set of acceptable routing layers, allowing an optimal route for a signal to be chosen in relation to the requirements of other signals.
Incorporating layer-dependent wire load information into the initial synthesis and layout steps results in an initial floorplan with improved timing performance. A method according to the invention thereby reduces the number of costly and time-consuming iterations between synthesis and layout steps by expediting timing closure.


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