Semiconductor device manufacturing: process – With measuring or testing – Optical characteristic sensed
Reexamination Certificate
1999-08-25
2001-07-24
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
With measuring or testing
Optical characteristic sensed
C438S007000, C430S030000
Reexamination Certificate
active
06265235
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the integrated circuit processing arts. It finds particular application in the sampling of small sections of photoresist for profile examination, and will be described with particular reference thereto. It should be appreciated, however, that the technique is also applicable to the examination of sections of a variety of microscopic topographical features.
BACKGROUND OF THE INVENTION
During many of the steps involved in the manufacture of integrated circuits, features are defined by photolithographic methods. Careful control of the features is often essential for good performance of the integrated circuit. The features are difficult to measure using conventional optical techniques. The features are small, often about 1 micrometer in cross section, and the feature edges are not always perfectly straight and vertical (i.e., perpendicular to the underlying substrate). Often, the feature edges are sloped or irregular along the length of the feature. Consequently, a precise definition of the terms “feature width” and “feature height” is difficult.
Various techniques have been developed for measuring the pitch and width of features on a substrate. These include the use of scanning electron microscopes (both high voltage, using energies of 15-30 kV, and low voltage, using energies of typically less than 2 kV), scanning probe microscopes (Atomic Force Microscopy, etc.), and optical microscopes. Combinations of these techniques are often employed.
In the case of integrated circuits, a section through the circuit, including the feature to be examined, is generally cut and the exposed cross section is subjected to the selected measurement technique or techniques. Alternatively, a portion of the substrate is gouged out of the wafer, carrying with it the topographical feature to be examined. One method of sectioning an integrated circuit includes the use of a Focused Ion Beam (FIB) tool. An FIB produces a finely focussed ion beam, such as a beam of gallium ions, which can be directed at the wafer.
These method of measuring feature geometry, or “metrology” have a number of disadvantages. First, the taking of a section through the entire wafer destroys the wafer on which the circuit is formed. As wafers are manufactured with increasingly large diameters (20 cm, and above) the costs of the wafers increase accordingly and sectioning also becomes more difficult. It is therefore desirable that a non-destructive testing method be developed.
Second, the sectioning process used to cut the section tends to change the cross section of the feature to be examined, especially in the case of relatively soft materials, such as photoresist. FIB is particularly damaging to the soft photoresist material, leading to deformation of the cross section. Thus, the dimensions measured may not correspond to those which were present on the wafer prior to sectioning.
Third, the taking of a section permits only one cross section of the feature to be examined at the end of the section. It does not allow a measurement of the changes in cross section along the length of the feature. Additionally, the section taken may not be representative of the feature as a whole.
The present invention provides a new and improved method for examining a feature which overcomes the above-referenced problems, and others.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a method of integrated circuit manufacturing is provided. The method includes forming a raised topographical feature on a substrate surface and removing a section of the feature from the substrate surface. The removal includes applying a force with a probe tip to a side of the feature to displace the section from the substrate surface and at least one adjacent portion of the feature and examining the removed section to determine whether a selected characteristic of the topographical feature meets a predetermined standard.
In accordance with one aspect of the present invention, a method of integrated circuit testing is provided. The method includes forming a raised topographical feature on a substrate surface and applying a force to a side of the topographical feature in a direction generally parallel with the substrate surface which causes a section of the feature to be severed from at least one adjacent remaining portion of the feature and disbonds the section from the substrate surface. The method further includes examining the removed section to determine whether a selected characteristic of the topographical feature meets a predetermined standard.
One advantage of the present invention is that it permits the evaluation of a feature of an integrated circuit without destruction of an entire wafer on which the circuit is formed.
Another advantage of the present invention is that it permits measurements of the change in feature dimensions along the length of the feature to be taken.
Another advantage of the present invention is that it permits all sides of the feature to be examined, including the surface in contact with the underlying substrate.
Still further advantages of the present invention will become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description of the preferred embodiments.
REFERENCES:
patent: 5338997 (1994-08-01), Benecke
patent: 5651574 (1997-07-01), Tanikawa et al.
patent: 5665199 (1997-09-01), Sahota et al.
patent: 5741614 (1998-04-01), Mc Coy et al.
patent: 5804460 (1998-09-01), Bindell et al.
patent: 6146913 (2000-11-01), Rafferty
Giannuzzi, et al., “Focused Ion Beam Milling and Micromanipulation Lift-Out for Site Specific Cross-Section TEM Specimen Preparation,” Materials Res. Soc., Symp. Proc. vol. 480 pp 19-27 (1997).
Houge Erik C.
Kane Brittin C.
McIntosh John M.
Molloy Simon J.
Vartuli Catherine
Estrada Michelle
Fay Sharpe Fagan Minnich & McKee LLP
Fourson George
Lucent Technologies - Inc.
LandOfFree
Method of sectioning of photoresist for shape evaluation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of sectioning of photoresist for shape evaluation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of sectioning of photoresist for shape evaluation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2486886