Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-07-08
2008-07-08
Lin, Sun James (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07398499
ABSTRACT:
A method of searching paths that are susceptible to electrostatic discharge (ESD) at the beginning of an integrated circuit (IC) design is disclosed that includes a circuit spreading out algorithm, a matrix closure algorithm, and a supernode algorithm. The found paths are required to satisfy conditions including that (a) they are connected from a gate of a transistor to a source or a drain thereof, and (b) the head node and the tail node of each path are pins of a top level of the IC. −1/0/1 matrix multiplication is employed by both the circuit spreading out algorithm and the matrix closure algorithm so as to obtain a result of node connections after a plurality of matrix self-multiplications.
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Gramacy,“Shortest Paths and Network Flow Algorithms for Electrostatic Discharge Analysis”, Jun. 2001, University of California at Santa Crus, Senior Thesis, pp. 1-50.
Cho Chao-Yi
Chu Chia-Chi
Feng Wu-Shiung
Lai Ming-Hong
Chang Gung University
Lin Sun James
Mersereau Mark A.
Nikolai & Mersereau , P.A.
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