Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-12-08
2002-05-14
Zarabian, Amir (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S303000
Reexamination Certificate
active
06387786
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This present invention relates to a method of forming a salicide. In particular, the present invention relates to a method of forming a salicide by siliciding a gate area prior to siliciding a source and drain area and/or spacer formation.
2. Description of Related Art
A conventional transistor comprises a source area, a drain area and a gate area between the source and drain areas.
SUMMARY
The present invention relates to a method of forming a self-aligned silicide (salicide) by siliciding a gate area prior to siliciding a source and drain area or spacer formation. The method improves transistor speed by lowering the leakage current in the source and drain areas and lowering the polysilicon sheet resistance of the gate. As a result of one embodiment of the present method, a silicide is formed over the gate area that is advantageously thicker than silicide formations over the source and drain areas. The silicide formations formed over the source and drain areas are advantageously shallow, such that the silicide formations do not impede the junction and cause current leakage.
One aspect of the invention relates to a method of forming a silicide. The method comprises conformally forming a first metal layer over a gate area and a gate dielectric layer. The gate dielectric layer covers a source area and a drain area. The method further comprises applying a first thermal anneal that causes the metal layer to at least partially react with the gate area to form a first silicide layer over the gate area. The method further comprises removing any unreacted metal from the first metal layer over the gate dielectric layer, and removing the gate dielectric layer over the source and drain areas. The method further comprises forming a second metal layer over the first silicide layer and the source and drain areas. The method further comprises applying a second thermal anneal, wherein the second thermal anneal causes (1) the second metal layer to further react with the gate area to enhance the first silicide layer, and (2) the second metal layer to at least partially react with the source and drain areas to form second and third silicide layers. The method further comprises removing any unreacted metal from the second metal layer.
Another aspect of the invention relates to a product made by the method above.
The present invention will be more fully understood upon consideration of the detailed description below, taken together with the accompanying drawings.
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“Manufacturability Issues related to Transient Thermal Annealing of Titanium Silicide Films in a Rapid Thermal Processor”, Shenai, K. IEEE Transactions on Semiconductor Manufacturing. vol. 4, No. 1, Feb., 1991, pp. 1-8.*
“Correlation of Film Thickness and Deposition Temperature with PAI and the Scalability of Ti-Salicide Technology to Sub-0.18 Tm Regime” Ho, C.; Karunasiri, S.; Chua, S.; Pey, K; Siah, S.; Lee, K.; Chan, L. Interconnect Tech. Conference, 1998, pp. 193-195.*
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Erhardt Jeff
Paton Eric
Advanced Micro Devices
Chen Alex C.
Owens Beth E.
Skjerven Morrill & MacPherson LLP
Zarabian Amir
LandOfFree
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