Method of salicide formation

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation

Reexamination Certificate

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Details

C438S655000, C438S664000, C438S683000

Reexamination Certificate

active

06399467

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This present invention relates to a method of forming a salicide. In particular, the present invention relates to a method of forming a salicide with a screening oxide.
2. Description of Related Art
A conventional transistor comprises a source area, a drain area and a gate area between the source and drain areas.
SUMMARY
The present invention relates to a method of forming a self-aligned silicide (salicide) with a screening oxide. The method improves transistor speed by lowering the leakage current in the source and drain areas and lowering the polysilicon sheet resistance of the gate. As a result of one embodiment of the present method, a silicide is formed over the gate area which is advantageously about two to three times thicker than silicide formations over the source and drain areas. The silicide formations formed over the source and drain areas are advantageously shallow, such that the silicide formations do not impede the junction and cause current leakage.
One aspect of the invention relates to a method of forming a silicide. The method comprises forming a metal layer over a gate area, a first oxide layer and a second oxide layer. The first oxide layer covers a source area and the second oxide layer covers a drain area. The method further comprises forming a capping layer over the metal layer. The capping layer comprises a material that can reduce an oxide. The method further comprises applying a first thermal anneal that causes the metal layer to at least partially react with the gate area to form a first silicide layer over the gate area. The method further comprises applying a second thermal anneal, wherein the second thermal anneal causes (1) the metal layer to further react with the gate area, (2) the material of the capping layer to diffuse through the metal layer and reduce the first and second oxide layers, and (3) the metal layer to at least partially react with the source and drain areas to form second and third suicide layers. The method further comprises removing the unreacted metal layer.
Another aspect of the invention relates to a product made by the method above.
The present invention will be more fully understood upon consideration of the detailed description below, taken together with the accompanying drawings.


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New Effect of Ti-Capping Lyer in Co Salicide Porcess Promising for Deep Sub-quarter Micron Technology, Ja-Hum Ku, et al., IEEE IITC, 1999, pp. 256-258.
The Influence of Capping Layer Type on Cobalt Salicide Formation in Films and Narrow Lines, P.R. Besser, A. Lauwers, N. Roelandts, K. Maex, W. Blum, R. Alvis, Stucchi, M. De Potter, Advanced Interconnect Process Development, Advanced Micro Devices, Sunnyvale, CA; IMEC; Submitted to 1998 Spring MRS Symp. Proc.: Advanced Interconnects and Contact Materials and Processes for Future ICs, 6 pages.

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