Fishing – trapping – and vermin destroying
Patent
1996-10-11
1997-07-15
Niebling, John
Fishing, trapping, and vermin destroying
437 29, 437 34, 437 56, 437200, 148DIG1, 148DIG3, 257274, H01L 21265
Patent
active
056482876
ABSTRACT:
A process for forming a MOS transistor having a salicide structure with a second gate spacers 36 and a source/drain/gate contact pads 32 33. A gate electrode 18 having first sidewall spacers 24 is formed on a substrate. Source and drain regions 28 are formed in the substrate. An amorphous silicon layer is formed over the substrate and patterned leaving the amorphous silicon layer over first sidewall spacers 24 and forming source/drain contact pads 33 over the source/drain regions and gate contact pads 32 over the gate electrode. Nitrogen ions are implanted vertically into the amorphous silicon layer 32 forming a nitrogen rich layer 34. The nitrogen rich layer 34 acts as an oxidation barrier source/drain an gate contact pads. The amorphous silicon layer 28 over the first sidewall spacer is oxidized using the nitrogen rich layer 34 as an oxidation barrier forming second gate spacers 36. A Ti layer is formed over the resultant surface. The substrate is rapid thermal annealed thereby forming titanium silicide 38 on the source/drain/gate contact pads. The contact pads eliminate silicide spiking and leakage. The second spacers eliminate stringer problem (i.e., shorting between the S/D and gate silicide contacts).
REFERENCES:
patent: 5322809 (1994-06-01), Moslehi
patent: 5391508 (1995-02-01), Matsuoka et al.
patent: 5529958 (1996-06-01), Yaoita
patent: 5585295 (1996-12-01), Wu
Peng Shie-Sen
Tsai Chao-Chieh
Niebling John
Pham Long
Saile George O.
Stoffel William J.
Taiwan Semiconductor Manufacturing Company , Ltd.
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