Method of routing in a programmable logic device

Details Method of routing in a programmable logic device Method of routing in a programmable logic device

2005-06-14

2005-06-14

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06907592

ABSTRACT:
A method is disclosed to efficiently route in a programmable logic device (PLD) such as a field-programmable gate array (FPGA). The method includes identifying a source and destination pair in a circuit design; determining multiple candidate paths to route a vector between the source and destination pair; and selecting one of the candidate paths for the vector route. Efficiency may be improved by using time-division multiplexing to route multiple connections through a PLD element.

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