Method of routing an integrated circuit

Details Method of routing an integrated circuit Method of routing an integrated circuit

1996-11-01

1999-12-21

Teska, Kevin J.

G06F 1750

Patent

active

060060247

ABSTRACT:
A method for automatically selecting tie styles used during the horizontal placement of substrate and well ties. A linear order of tie styles is determined (2422). Ties are placed horizontally in the layout based upon an initial tie style (2424). Route and compact layout components (2426). If the layout has satisfied the tie coverage rules (2428) the tie style selection process is complete. Otherwise, contacts, vias and ties are added where possible (2430). If the layout has now satisfied the tie coverage rules (2432) tie style selection process is complete. If not, the next tie style is chosen from the linear order (2434). The process continues by placing (2424), routing and compacting components (2426) with the new tie style, until the cell satisfies the tie coverage rules.

REFERENCES:
patent: 5313079 (1994-05-01), Brasen et al.
patent: 5666288 (1997-09-01), Jones et al.
patent: 5689432 (1997-11-01), Blaauw et al.
patent: 5764533 (1998-06-01), DeDood
Virtuoso Layout Synthesizer (LAS) User Guide Version 4.2-Cadence Design Systems-Oct. 1991.

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