Low voltage biCMOS circuit having ECL and TTL input buffers and

Details Low voltage biCMOS circuit having ECL and TTL input buffers and Low voltage biCMOS circuit having ECL and TTL input buffers and

1993-01-15

1994-04-05

Hudspeth, David R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072961, 307443, 307446, H03K 19092

Patent

active

053008332

ABSTRACT:
In the conventional configuration, when using circuits with different logical amplitude levels in mixture, the level converter circuit has been necessarily required, and this has been an element preventing the speeding up. Also when holding the ECL interface and the TTL interfaces in common, the level converter circuit is useless and the total size gets larger. In the present invention, for the semiconductor circuit mixed with the input buffer 1 receiving the signal amplitude voltage of the ECL interface, the input buffer 3 receiving the signal amplitude voltage of the TTL interface, and the MIS or BiMIS driver 2, the level converter circuit is not required by holding each signal amplitude voltage in Common, and it can be speeded up as much as the delayed time caused by the level converter circuit. And the total size of the switching between the TTL input buffer 3 and the ECL input buffer 1 can be reduced because there is no level converter circuit, and the ECL interface and the TTL interface can be easily mixed.

REFERENCES:
patent: 4879480 (1989-11-01), Suzuki et al.
patent: 4939393 (1990-07-01), Petty
patent: 4984202 (1991-01-01), Kawahara et al.
patent: 5122692 (1992-06-01), Seki
patent: 5132573 (1992-07-01), Tsuru et al.

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