Method of resist stripping over low-k dielectric material

Details Method of resist stripping over low-k dielectric material Method of resist stripping over low-k dielectric material

2002-01-02

2003-11-18

Goudreau, George (Department: 1763)

Cleaning and liquid contact with solids

Processes

Including application of electrical radiant or wave energy...

C438S725000, C438S714000, C438S710000, C438S737000, C438S726000, C438S727000, C216S063000, C216S069000, C216S071000

Reexamination Certificate

active

06647994

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to a method of resist stripping from a substrate containing low-k dielectric material.
(2) Description of Related Art
In the fabrication of semiconductor integrated circuits device element geometries have shrunk to and below 0.5 microns. At the same time the demands upon the interlevel dielectric layers and the conductive materials used for device interconnections have become more stringent. The interlevel dielectric layers must fill gaps with higher aspect ratios and must provide lower dielectric constants in order to reduce both interlevel and intra-level capacitance. Capacitance markedly increases when the spacing between conductive elements decreases below 0.5 microns and it becomes imperative that low dielectric constant material be used as both the interlevel and intra-level insulating material. Circuit speed is a function of the RC constant of the integrated circuit devices, where R is the resistance of the conducting portions of the integrated circuit and C is the capacitance, both interlevel and intra-level, of the integrated circuit structure. Therefore, it is desirable that the RC constant be low, so a high conductivity material, such as copper is preferred for the interconnection elements of the integrated circuit and a low dielectric constant material, such as OSG (Organic Silicate Glass) or HSQ (hydrogen silsesquioxane) is preferred as the interlevel and intra-level insulating layers. One factor in achieving a low dielectric constant in OSG is the more porous structure of OSG, as generated by the organic doping during deposition or formation of the OSG layers. It is known that porous dielectrics, and particularly OSG dielectric layers, are subject to attack and damage by photoresist stripping processes in plasmas containing O
2
. When vertical structures, etched in OSG, are subjected to O
2
containing plasmas, as would be the case when stripping a photoresist mask from the top surface of the OSG structure, the O
2
containing plasma attacks the sidewalls of the OSG structure and causes a loss of vertical profile in the OSG structure. This loss of vertical profile (called bowing) in the etched OSG layer results in the loss of OSG material and produces a structure that is more difficult to fill with a subsequently deposited layer, such as a conductive layer comprising copper or tungsten. Filling of etched trenches and etched features in dielectric layers by deposition of a conducting layer over the etched trenches and features, followed by removal of unwanted conductive material from the top surface of the dielectric layer by CMP (Chemical Mechanical Polishing) is known as the Damascene process.
Therefore, an important challenge in using OSG as a low dielectric constant insulator in multilevel integrated circuit structures is to develop a photoresist stripping process which does not attack or damage an underlying OSG layer or profiles etched in the OSG layer.
Numerous processes have been developed for stripping photoresist. U.S. Pat. No. 5,262,279 entitled “Dry Process For Stripping Photoresist From A Polyimide Surface” granted Nov. 16, 1993 to Chi-Hwa Tsang et al. describes a dry process for stripping photoresist from a polyimide surface formed on a semiconductor substrate. The reactive stripping agent comprises activated oxygen radicals generated in a microwave plasma.
U.S. Pat. No. 5,057,187 entitled “Ashing Method For Removing An Organic Film On A Substance Of A Semiconductor Device Under Fabrication” granted Oct. 15, 1991 to Keisuke Shinagawa et al. shows a method of removing a resist material by plasma ashing in a plasma comprising O
2
, H
2
O and N
2
. Alternately the stripping plasma comprises O
2
, H
2
O and CF
4
or O
2
, H
2
and N
2
.
U.S. Pat. No. 6,105,588 entitled “Method Of Resist Stripping During Semiconductor Device Fabrication” granted Aug. 22, 2000 to Li Li et al. describes a method of resist stripping in gaseous plasmas formed in gases or mixtures of gases comprising: 1. NH
3
; 2. NH
3
and N
2
; 3. O
2
, NH
3
, H
2
O and N
2
; or 4. O
2
, NH
3
, H
2
O, CF
4
and N
2
.
The present invention is directed to a novel method of stripping a photoresist mask from the surface of an OSG layer or from the surface of an OSG layer having an etched vertical profile formed therein. The method of the present invention causes stripping of a photoresist mask without attack or damage to the OSG layer or without attack or damage to the sidewalls of the etched vertical profile of structures etched in the OSG layer.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide an improved method of photoresist stripping for use during fabrication of semiconductor integrated circuits.
A more specific object of the present invention is to provide an improved method of photoresist stripping for use during fabrication of semiconductor integrated circuits, which use porous low-k dielectric materials as the interlevel and intra-level insulating layers.
Another object of the present invention is to provide an improved method of photoresist stripping for use during fabrication of semiconductor integrated circuits, which use porous oxides, such as OSG, as the low-k dielectric material in interlevel and intra-level insulating layers.
In accordance with the present invention, the above and other objectives are realized by using a method of photo-resist stripping during semiconductor device fabrication, the method comprising: providing a semiconductor substrate with a photoresist material formed thereon; placing the semi-conductor substrate in a chamber having therein a plasma generating power source; passing a gaseous mixture comprising NH
3
and CO through said chamber; applying power to said plasma generating power source to cause ionization of said gaseous mixture; and directing the ionized gas mixture at the semiconductor substrate to cause stripping of said photo-resist material.
In a second embodiment of the present invention, the above and other objectives are realized by using a method of stripping photoresist applied over a layer of low-k dielectric material during semiconductor device fabrication, the method comprising: providing a semiconductor substrate with a photoresist material applied over a layer of low-k dielectric material formed on the semiconductor substrate; placing the semiconductor substrate in a chamber having therein a plasma generating power source; passing a gaseous mixture comprising NH
3
and CO through said chamber; applying power to said plasma generating power source to cause ionization of said gaseous mixture; and directing the ionized gas mixture at the semiconductor substrate to cause stripping of said photoresist material applied over said layer of low-k dielectric material.
In yet a third embodiment of the present invention, the above and other objectives are realized by using a method of fabricating a vertically etched structure in a layer of low-k dielectric material applied to a semiconductor substrate, comprising the steps of: providing the semiconductor substrate having a layer of low-k dielectric material applied thereon; applying a patterned layer of photoresist onto said layer of low-k dielectric material; etching said layer of low-k dielectric material to form vertical sidewall trenches and features in said low-k dielectric material; and stripping said patterned layer of photoresist in a plasma generated in a gaseous mixture of NH
3
and CO.


REFERENCES:
patent: 5057187 (1991-10-01), Shinagawa et al.
patent: 5262279 (1993-11-01), Tsang et al.
patent: 6105588 (2000-08-01), Li et al.
patent: 6413877 (2002-07-01), Annapragada
patent: 2002/0111041 (2002-08-01), Annapragada et al.
patent: 2002/0119664 (2002-08-01), Annapragada et al.
patent: 59-086224 (1984-05-01), None
patent: 06-132259 (1994-05-01), None

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