Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1998-01-26
2000-09-05
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 7, 714 8, 714710, 365200, G11C 1140
Patent
active
061158283
ABSTRACT:
A memory having a plurality of memory cells and a plurality of redundant memory cells accesses a redundant memory cell in lieu of a failed memory cell. The memory is tested for failed memory cells. Addresses of detected failed memory cells are stored in a first set of registers, and addresses of redundant memory cells are stored in a second, corresponding set of registers. An external address is compared with the address stored in the first set of registers and if there is a match, the corresponding redundant memory cell address stored in the second register set is used to access the memory, in lieu of the external memory address.
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Nishii Toshiyuki
Takeshige Masayuki
Tsutsumi Tetsuji
Beausoliel, Jr. Robert W.
Bonzo Bryce
Fujitsu Limited
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