Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2001-09-07
2003-02-18
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S706000
Reexamination Certificate
active
06521547
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a method of repairing a low dielectric constant (low k) material layer, and more specifically, to a method of repairing damage to the low k material layer caused by an oxygen plasma ashing process by using a solution of alkyl silane comprising an alkyl group and a halo substituent to remove Si—OH bonds formed in the low k layer during the oxygen plasma ashing process.
2. Description of the Prior Art
With a decreasing size of semiconductor devices and an increase in integrated circuit (IC) density, RC time delay effects, produced between the metal wires, seriously affect IC operation and performance, and reduce IC operating speed. RC time delay effects are more obvious especially when the line width is reduced to 0.25 &mgr;m, or even 0.13 &mgr;m in a semiconductor process.
RC time delay effects produced between metal wires are a product of an electrical resistance (R) of the metal wires and a parasitic capacitance (C) of a dielectric layer between the metal wires. Normally RC time delay effects can be reduced by either using conductive materials with a lower resistance such as a metal wire, or reducing the parasitic capacitance of the dielectric layer between metal wires. In the approach of using a metal wire with a lower resistance, copper interconnect technology replaces the traditional Al:Cu(0.5%) alloy fabrication process and is a necessary tendency in multilevel metallization processes. Due to copper having a low resistance (1.67 &mgr;&OHgr;-cm) and higher current density load without electro-migration in the Al/Cu alloy, the parasitic capacitance between metal wires and connection levels of metal wires is reduced. However, reducing RC time delay produced between metal wires by only using copper interconnect technology is not enough. Also, some fabrication problems of copper interconnect technology need to be solved. Therefore, it is more and more important to reduce RC time delay by the approach of reducing the parasitic capacitance of the dielectric layer between metal wires.
Additionally, the parasitic capacitance of a dielectric layer is related to the dielectric constant of the dielectric layer. As the dielectric constant of the dielectric layer decreases, the parasitic capacitance of the dielectric layer decreases. Traditional silicon dioxide, having a dielectric constant of 3.9, cannot meet the requirement of 0.13 &mgr;m semiconductor processes, so some new low k materials, such as polyimide (PI), FLARE™, FPI, PAE-2, PAE-3 or LOSP are thereby consecutively proposed. However, these low k materials are composed of carbon, hydrogen and oxygen, and have significantly different properties than those of traditional silicon dioxide used in etching or adhering with other materials. Most of these low k materials have some disadvantages such as poor adhesion and poor thermal stability, so they cannot properly integrate into current IC fabrication processes.
Therefore, another kind of low k dielectric layer, such as hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ) and HOSP,having dielectric constants of 2.8, 2.7 and 2.5 respectively, which uses the silicon dioxide as a base, and adds some carbon and hydrogen elements, is needed. These silicon based low k materials have potential in the future since properties of these materials resemble traditional silicon dioxide and can be easily integrated into the current IC fabrication process.
Please refer to
FIG. 1
to
FIG. 3
of schematic views of removing a photoresist layer according the prior art. As shown in
FIG. 1
, a semiconductor wafer
10
comprises a silicon substrate
12
and a low k material layer
14
, composed of SiO
2
-based materials such as hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ) and HOSP,formed on the silicon substrate
12
by performing a chemical vapor deposition (CVD) process or a spin-on process.
As shown in
FIG. 2
, a photoresist layer
16
is coated on the low k material layer
14
and an opening
18
is formed in the photoresist layer
16
to expose portions of the low k material layer
14
thereafter. By performing a dry etching process to etch the low k material layer
14
through the opening
18
, a pattern in the photoresist layer
16
is transferred to the low k material layer
14
.
As shown in
FIG. 3
, a stripping process, comprising an ashing process and a dipping process, is performed. By performing the ashing process with an oxygen plasma supply, gaseous carbon dioxide and water vapor are formed by a reaction between the oxygen plasma and carbon and hydrogen atoms in the photoresist layer
16
. The photoresist layer
16
is thus stripped. Finally, the semiconductor wafer
10
is dipped in the photoresist stripper to completely remove the photoresist layer
16
.
However, when patterning a dielectric layer composed of SiO
2
-based low k materials, such as HSQ, MSQ or HOSP, the dielectric layer suffers some damage during an etching or stripping process. Since a dry oxygen plasma ashing process and a wet stripper are frequently employed in the stripping process to remove a photoresist layer, bonds in a surface of the dielectric layer are easily broken by oxygen plasma bombardment and react with oxygen ions as well as with wet stripper to form Si—OH bonds. Since the Si—OH bonds absorb water moisture, having a dielectric constant of approximately 78, the dielectric constant and leakage current of the dielectric layer are consequently increased, and a poisoned via phenomenon occurs, thereby seriously affecting the reliability of products.
SUMMARY OF INVENTION
It is therefore a primary object of the present invention to provide a method of repairing a low dielectric constant (low k) material layer so as to prevent an increase in either dielectric constant or current leakage of the low k material layer.
According to the claimed invention, a method of repairing a low k material layer starts with providing a semiconductor wafer with a silicon oxide based (SiO
2
-based) low k material layer. A hydrogen plasma pretreatment is performed on the low k material to reinforce the low k material layer. A photoresist layer is then coated on the low k material layer and an opening is formed in the photoresist layer to expose portions of the low k material layer thereafter. By dry etching the low k material layer through the opening, a pattern in the photoresist layer is transferred to the low k material layer. An oxygen plasma ashing process is then performed to remove the photoresist layer. Finally, by contacting the low k material layer with a solution of alkyl silane comprising an alkyl group and a halo substituent, Si—OH bonds formed in the low k layer during the oxygen plasma ashing process are removed. Damage to the low k material layer caused by the oxygen plasma ashing process is thus repaired. Simultaneously, a surface of the low k material layer is enhanced to a hydrophobic surface to prevent moisture adhering to the surface of the low k material layer.
It is an advantage of the present invention against the prior art that Si—OH bonds formed in the low k material layer
44
due to the plasma ashing process are eliminated by contacting the low k material layer with a solution of alkyl silane comprising an alkyl group and a halo substituent. Damage to the low k material layer caused by the plasma ashing process is thus repaired. In addition, the method provided in the present invention can further change the surface of the low k material layer from hydrophilic to hydrophobic. Therefore, the hydrophobic surface can prevent moisture absorption in the following process environment. Consequently, an increase in either the dielectric constant or current leakage of the low k material layer
44
is prevented as well.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the multiple figures and drawings.
REFERENCES:
patent: 6162838 (2000-12-0
Chang Ting-Chang
Liu Po-Tsun
Mor Yi-Shien
Hsu Winston
Nhu David
United Microelectronics Corp.
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