Method of removing gated clocks from the clock nets of a netlist

Details Method of removing gated clocks from the clock nets of a netlist Method of removing gated clocks from the clock nets of a netlist

1993-02-26

1995-09-19

Ramirez, Ellis B.

Boots, shoes, and leggings

364580, 371222, G06G 748, G06F 1700

Patent

active

054522390

ABSTRACT:
An emulation system and method that reduces or eliminates the number of timing errors such as hold time violations when implementing a netlist description of an integrated circuit. The emulation system comprises a plurality of reprogrammable logic circuits and a plurality of reprogrammable interconnect circuits. The netlist description is optimized to reduce the number of timing violations by removing the occurences of gated clocks from the netlist, partitioning the netlist description by taking into account the occurence of timing violations and ensuring that retain state nets are implemented properly.

REFERENCES:
patent: 4306286 (1981-12-01), Cocke et al.
patent: 4578761 (1986-03-01), Gray
patent: 4656580 (1987-04-01), Hitchcock, Sr. et al.
patent: 5109353 (1992-04-01), Sample et al.

Affiliated with

Also associated with

Rating

Method of removing gated clocks from the clock nets of a netlist does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of removing gated clocks from the clock nets of a netlist, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of removing gated clocks from the clock nets of a netlist will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1833772