Method of regulating a digital phase-locked circuit, and a digit

Details Method of regulating a digital phase-locked circuit, and a digit Method of regulating a digital phase-locked circuit, and a digit

1996-11-25

1999-12-28

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375376, 327147, 327160, H03D 324, H03L 706, H03L 700

Patent

active

060091339

ABSTRACT:
A digital phase-locked loop (1) has a counter (4) which counts pulses from a voltage controlled oscillator (8). The counter (4) is latched periodically with a period which is determined by an input signal (I) to the counter (4). The latched value is supplied to a compensation unit (5) which deducts a value which approximately corresponds to half the count counted by the counter circuit (4) when the phase lock is locked correctly. The compensated counts are supplied from the output of the compensation unit (5) to an integrator (6) and counter (9) which applies a control signal to the voltage controlled oscillator (8) via a D/A converter.

REFERENCES:
patent: 4864253 (1989-09-01), Zwack
patent: 5105160 (1992-04-01), Summers

Affiliated with

Also associated with

Rating

Method of regulating a digital phase-locked circuit, and a digit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of regulating a digital phase-locked circuit, and a digit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of regulating a digital phase-locked circuit, and a digit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2387501