Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2002-06-20
2004-05-04
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S185220
Reexamination Certificate
active
06731557
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior European Application No. 01830418.8, filed Jun. 21, 2001, the disclosure of which is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of refreshing an electrically erasable and programmable non-volatile memory.
2. Description of Related Art
Non-volatile memories, which can be erased and programmed electrically, are commonly used in several applications when the data stored in the memory must be preserved even if a power supply is off. For example, a flash memory is a particular type of E
2
PROM, wherein each memory cell consists of a single transistor (typically a floating gate MOS transistor). The transistors of the flash memory are programmed by injecting an electric charge into their floating gates. Conversely, the transistors are erased by discharging their floating gates; generally, the flash memory is erased in blocks (or sectors) formed by a few thousands of transistors. The electric charge in the floating gate of each transistor modifies its threshold voltage, so as to define different logic values. This results in a very simple structure of the flash memory, which can be manufactured at low cost and with high density. As a consequence, the flash memory is well suited to a number of end-product applications, such as PCs (Personal Computers), cellular phones, automotive devices, digital still cameras, and the like.
Data retention is one of the most important problems of the flash memories. In fact, the transistors are subjected to different electric stresses during operation of the flash memory; these stresses may cause injection of electric charge into their floating gates (with an undesired programming of the transistors), or they may cause loss of the electric charge stored therein (with an undesired erasure of the transistors).
This problem is particular acute in modern flash memories, which feature a very thin oxide layer. Moreover, the problem is exacerbated in multilevel flash memories wherein the gap between reference voltages defining adjacent logic values is strongly reduced (down to 0.3 V); in this case, even a small drift of the threshold voltage of the transistor (for example, of 0.1 V) may change its logic value.
In order to prevent any loss of data stored in the flash memory, a refreshing procedure may be carried out periodically. The refreshing procedures known in the art require the steps of copying a sector of the flash memory onto a volatile memory, erasing the whole sector, and then restoring the data from the volatile memory; therefore, any power supply cut during the refreshing procedure may cause a loss of data stored in the volatile memory and then the impossibility of restoring the data onto the flash memory.
Different architectures allowing each single transistor to be selectively erased have been also proposed. For example, the U.S. Pat. No. 6,160,739, discloses a flash memory with source lines (coupled to sources of the transistors of corresponding columns) that extend perpendicularly to word lines (coupled to control gates of the transistors of corresponding rows). In this way, each couple source line/word line identifies a single transistor, which can be erased individually applying suitable voltages to the corresponding source line and word line.
In a different architecture, known as Virtual Ground, each bit line is connected to an active area (drain or source) of the transistors of two adjacent columns, so as to be used alternatively for contacting the drain terminals or the source terminals of the transistors.
Another solution is disclosed in the U.S. Pat. No. 5,656,840, and consists of associating a select transistor to each memory cell.
However, none of the solutions proposed in the prior art in any way addresses the data retention problem described in the foregoing. Particularly, the cited documents are completely silent on any refreshing procedure of the flash memory.
Accordingly, a need exists to overcome the above-mentioned drawbacks and to provide a method of refreshing an electrically erasable and programmable non-volatile memory.
SUMMARY OF THE INVENTION
Briefly, the present invention provides a method of refreshing an electrically erasable and programmable non-volatile memory having a plurality of memory cells, the method including the steps of: verifying whether a memory cell has drifted from a correct condition (i.e., a predetermined voltage and/or predetermined voltage range), and individually restoring the correct condition of the memory cell if the result of the verification is positive.
Moreover, the present invention also provides a corresponding electrically erasable and programmable non-volatile memory.
REFERENCES:
patent: 5250831 (1993-10-01), Ishii
patent: 5656840 (1997-08-01), Yang
patent: 6160739 (2000-12-01), Wong
patent: 6194759 (2001-02-01), Sano et al.
European Search report dated Nov. 22, 2001 for European Appln. No. 01830418.8.
Fleit Kain Gibbons Gutman Bongini & Bianco P.L.
Gibbons Jon A.
Jorgenson Lisa K.
STMicroelectronics S.r.l.
Tran M.
LandOfFree
Method of refreshing an electrically erasable and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of refreshing an electrically erasable and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of refreshing an electrically erasable and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3217426